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Commit 5792ab2a authored by Sonic Zhang's avatar Sonic Zhang Committed by Mike Frysinger
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Blackfin: MPU: handle caches for reserved memory 



We weren't handling the user-specified cache behavior for the reserved
memory regions (via mem=/max_mem=).  The no-MPU code already takes care
of this, so add support to the MPU code as well.

Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent d94a1aa4

arch/blackfin/kernel/cplb-mpu/cplbmgr.c

+5 −1
Original line number Diff line number Diff line
@@ -132,6 +132,8 @@ static noinline int dcplb_miss(unsigned int cpu) 
			return CPLB_PROT_VIOL;

	} else if (addr >= _ramend) {

		d_data |= CPLB_USER_RD | CPLB_USER_WR;

		if (reserved_mem_dcache_on)

			d_data |= CPLB_L1_CHBL;

	} else {

		mask = current_rwx_mask[cpu];

		if (mask) {
@@ -231,6 +233,8 @@ static noinline int icplb_miss(unsigned int cpu) 
		    return CPLB_PROT_VIOL;

	} else if (addr >= _ramend) {

		i_data |= CPLB_USER_RD;

		if (reserved_mem_icache_on)

			i_data |= CPLB_L1_CHBL;

	} else {

		/*

		 * Two cases to distinguish - a supervisor access must