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Commit 5746cc2a authored by John W. Linville's avatar John W. Linville
Browse files

Merge branch 'master' of...

parents f55aa836 a64e1a45
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+10 −2
Original line number Diff line number Diff line
@@ -358,6 +358,14 @@ static void ath9k_hw_init_config(struct ath_hw *ah)

	ah->config.rx_intr_mitigation = true;

	if (AR_SREV_9300_20_OR_LATER(ah)) {
		ah->config.rimt_last = 500;
		ah->config.rimt_first = 2000;
	} else {
		ah->config.rimt_last = 250;
		ah->config.rimt_first = 700;
	}

	/*
	 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
	 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
@@ -1876,8 +1884,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
		REG_WRITE(ah, AR_OBS, 8);

	if (ah->config.rx_intr_mitigation) {
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
	}

	if (ah->config.tx_intr_mitigation) {
+2 −0
Original line number Diff line number Diff line
@@ -310,6 +310,8 @@ struct ath9k_ops_config {
	u8 max_txtrig_level;
	u16 ani_poll_interval; /* ANI poll interval in ms */
	u16 hw_hang_checks;
	u16 rimt_first;
	u16 rimt_last;

	/* Platform specific config */
	u32 aspm_l1_fix;
+1 −1
Original line number Diff line number Diff line
@@ -524,7 +524,7 @@ void ath9k_tasklet(unsigned long data)
			 * successfully after a GTT interrupt, the GTT counter
			 * gets reset to zero here.
			 */
			/* sc->gtt_cnt = 0; */
			sc->gtt_cnt = 0;

			ath_tx_edma_tasklet(sc);
		} else {
+2 −2
Original line number Diff line number Diff line
@@ -821,10 +821,10 @@ void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr)
		 * channel number in b43. */
		if (chanstat & B43_RX_CHAN_5GHZ) {
			status.band = IEEE80211_BAND_5GHZ;
			status.freq = b43_freq_to_channel_5ghz(chanid);
			status.freq = b43_channel_to_freq_5ghz(chanid);
		} else {
			status.band = IEEE80211_BAND_2GHZ;
			status.freq = b43_freq_to_channel_2ghz(chanid);
			status.freq = b43_channel_to_freq_2ghz(chanid);
		}
		break;
	default:
+3 −1
Original line number Diff line number Diff line
@@ -289,13 +289,15 @@ static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 */
void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
{
	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
	u32 reg = 0;
	int txq_id = txq->q.id;

	if (txq->need_update == 0)
		return;

	if (trans->cfg->base_params->shadow_reg_enable) {
	if (trans->cfg->base_params->shadow_reg_enable ||
	    txq_id == trans_pcie->cmd_queue) {
		/* shadow register enabled */
		iwl_write32(trans, HBUS_TARG_WRPTR,
			    txq->q.write_ptr | (txq_id << 8));
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