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Commit 55a4e789 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge branch 'pm-hwmod-i2c' of... 

Merge branch 'pm-hwmod-i2c' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-for-linus
parents 9c7bc451 27b1fec2

arch/arm/mach-omap2/cm-regbits-24xx.h

+4 −0
Original line number Diff line number Diff line
@@ -126,8 +126,12 @@ 
#define OMAP24XX_ST_HDQ_MASK				(1 << 23)

#define OMAP2420_ST_I2C2_SHIFT				20

#define OMAP2420_ST_I2C2_MASK				(1 << 20)

#define OMAP2430_ST_I2CHS1_SHIFT			19

#define OMAP2430_ST_I2CHS1_MASK				(1 << 19)

#define OMAP2420_ST_I2C1_SHIFT				19

#define OMAP2420_ST_I2C1_MASK				(1 << 19)

#define OMAP2430_ST_I2CHS2_SHIFT			20

#define OMAP2430_ST_I2CHS2_MASK				(1 << 20)

#define OMAP24XX_ST_MCBSP2_SHIFT			16

#define OMAP24XX_ST_MCBSP2_MASK				(1 << 16)

#define OMAP24XX_ST_MCBSP1_SHIFT			15

arch/arm/mach-omap2/omap_hwmod_2420_data.c

+142 −3
Original line number Diff line number Diff line
@@ -16,11 +16,13 @@ 
#include <plat/cpu.h>

#include <plat/dma.h>

#include <plat/serial.h>

#include <plat/i2c.h>

#include <plat/omap24xx.h>



#include "omap_hwmod_common_data.h"



#include "prm-regbits-24xx.h"

#include "cm-regbits-24xx.h"

#include "prm-regbits-24xx.h"



/*

 * OMAP2420 hardware module integration data
@@ -77,6 +79,8 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod; 
static struct omap_hwmod omap2420_uart1_hwmod;

static struct omap_hwmod omap2420_uart2_hwmod;

static struct omap_hwmod omap2420_uart3_hwmod;

static struct omap_hwmod omap2420_i2c1_hwmod;

static struct omap_hwmod omap2420_i2c2_hwmod;



/* L4_CORE -> L4_WKUP interface */

static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
@@ -139,6 +143,45 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* I2C IP block address space length (in bytes) */

#define OMAP2_I2C_AS_LEN		128



/* L4 CORE -> I2C1 interface */

static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {

	{

		.pa_start	= 0x48070000,

		.pa_end		= 0x48070000 + OMAP2_I2C_AS_LEN - 1,

		.flags		= ADDR_TYPE_RT,

	},

};



static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {

	.master		= &omap2420_l4_core_hwmod,

	.slave		= &omap2420_i2c1_hwmod,

	.clk		= "i2c1_ick",

	.addr		= omap2420_i2c1_addr_space,

	.addr_cnt	= ARRAY_SIZE(omap2420_i2c1_addr_space),

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* L4 CORE -> I2C2 interface */

static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {

	{

		.pa_start	= 0x48072000,

		.pa_end		= 0x48072000 + OMAP2_I2C_AS_LEN - 1,

		.flags		= ADDR_TYPE_RT,

	},

};



static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {

	.master		= &omap2420_l4_core_hwmod,

	.slave		= &omap2420_i2c2_hwmod,

	.clk		= "i2c2_ick",

	.addr		= omap2420_i2c2_addr_space,

	.addr_cnt	= ARRAY_SIZE(omap2420_i2c2_addr_space),

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* Slave interfaces on the L4_CORE interconnect */

static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {

	&omap2420_l3_main__l4_core,
@@ -150,6 +193,8 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { 
	&omap2_l4_core__uart1,

	&omap2_l4_core__uart2,

	&omap2_l4_core__uart3,

	&omap2420_l4_core__i2c1,

	&omap2420_l4_core__i2c2

};



/* L4 CORE */
@@ -418,6 +463,100 @@ static struct omap_hwmod omap2420_uart3_hwmod = { 
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

};



/* I2C common */

static struct omap_hwmod_class_sysconfig i2c_sysc = {

	.rev_offs	= 0x00,

	.sysc_offs	= 0x20,

	.syss_offs	= 0x10,

	.sysc_flags	= SYSC_HAS_SOFTRESET,

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class i2c_class = {

	.name		= "i2c",

	.sysc		= &i2c_sysc,

};



static struct omap_i2c_dev_attr i2c_dev_attr;



/* I2C1 */



static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {

	{ .irq = INT_24XX_I2C1_IRQ, },

};



static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {

	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },

	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },

};



static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {

	&omap2420_l4_core__i2c1,

};



static struct omap_hwmod omap2420_i2c1_hwmod = {

	.name		= "i2c1",

	.mpu_irqs	= i2c1_mpu_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),

	.sdma_reqs	= i2c1_sdma_reqs,

	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),

	.main_clk	= "i2c1_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP2420_EN_I2C1_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,

		},

	},

	.slaves		= omap2420_i2c1_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_i2c1_slaves),

	.class		= &i2c_class,

	.dev_attr	= &i2c_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

	.flags		= HWMOD_16BIT_REG,

};



/* I2C2 */



static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {

	{ .irq = INT_24XX_I2C2_IRQ, },

};



static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {

	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },

	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },

};



static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {

	&omap2420_l4_core__i2c2,

};



static struct omap_hwmod omap2420_i2c2_hwmod = {

	.name		= "i2c2",

	.mpu_irqs	= i2c2_mpu_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(i2c2_mpu_irqs),

	.sdma_reqs	= i2c2_sdma_reqs,

	.sdma_reqs_cnt	= ARRAY_SIZE(i2c2_sdma_reqs),

	.main_clk	= "i2c2_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP2420_EN_I2C2_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,

		},

	},

	.slaves		= omap2420_i2c2_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2420_i2c2_slaves),

	.class		= &i2c_class,

	.dev_attr	= &i2c_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),

	.flags		= HWMOD_16BIT_REG,

};



static __initdata struct omap_hwmod *omap2420_hwmods[] = {

	&omap2420_l3_main_hwmod,

	&omap2420_l4_core_hwmod,
@@ -428,6 +567,8 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { 
	&omap2420_uart1_hwmod,

	&omap2420_uart2_hwmod,

	&omap2420_uart3_hwmod,

	&omap2420_i2c1_hwmod,

	&omap2420_i2c2_hwmod,

	NULL,

};
@@ -435,5 +576,3 @@ int __init omap2420_hwmod_init(void) 
{

	return omap_hwmod_init(omap2420_hwmods);

}

arch/arm/mach-omap2/omap_hwmod_2430_data.c

+153 −2
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ 
#include <plat/cpu.h>

#include <plat/dma.h>

#include <plat/serial.h>

#include <plat/i2c.h>

#include <plat/omap24xx.h>



#include "omap_hwmod_common_data.h"
@@ -77,6 +79,47 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod; 
static struct omap_hwmod omap2430_uart1_hwmod;

static struct omap_hwmod omap2430_uart2_hwmod;

static struct omap_hwmod omap2430_uart3_hwmod;

static struct omap_hwmod omap2430_i2c1_hwmod;

static struct omap_hwmod omap2430_i2c2_hwmod;



/* I2C IP block address space length (in bytes) */

#define OMAP2_I2C_AS_LEN		128



/* L4 CORE -> I2C1 interface */

static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {

	{

		.pa_start	= 0x48070000,

		.pa_end		= 0x48070000 + OMAP2_I2C_AS_LEN - 1,

		.flags		= ADDR_TYPE_RT,

	},

};



static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {

	.master		= &omap2430_l4_core_hwmod,

	.slave		= &omap2430_i2c1_hwmod,

	.clk		= "i2c1_ick",

	.addr		= omap2430_i2c1_addr_space,

	.addr_cnt	= ARRAY_SIZE(omap2430_i2c1_addr_space),

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* L4 CORE -> I2C2 interface */

static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {

	{

		.pa_start	= 0x48072000,

		.pa_end		= 0x48072000 + OMAP2_I2C_AS_LEN - 1,

		.flags		= ADDR_TYPE_RT,

	},

};



static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {

	.master		= &omap2430_l4_core_hwmod,

	.slave		= &omap2430_i2c2_hwmod,

	.clk		= "i2c2_ick",

	.addr		= omap2430_i2c2_addr_space,

	.addr_cnt	= ARRAY_SIZE(omap2430_i2c2_addr_space),

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* L4_CORE -> L4_WKUP interface */

static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -418,6 +461,114 @@ static struct omap_hwmod omap2430_uart3_hwmod = { 
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),

};



/* I2C common */

static struct omap_hwmod_class_sysconfig i2c_sysc = {

	.rev_offs	= 0x00,

	.sysc_offs	= 0x20,

	.syss_offs	= 0x10,

	.sysc_flags	= (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class i2c_class = {

	.name		= "i2c",

	.sysc		= &i2c_sysc,

};



static struct omap_i2c_dev_attr i2c_dev_attr;



/* I2C1 */



static struct omap_i2c_dev_attr i2c1_dev_attr = {

	.fifo_depth	= 8, /* bytes */

};



static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {

	{ .irq = INT_24XX_I2C1_IRQ, },

};



static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {

	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },

	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },

};



static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {

	&omap2430_l4_core__i2c1,

};



static struct omap_hwmod omap2430_i2c1_hwmod = {

	.name		= "i2c1",

	.mpu_irqs	= i2c1_mpu_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),

	.sdma_reqs	= i2c1_sdma_reqs,

	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),

	.main_clk	= "i2chs1_fck",

	.prcm		= {

		.omap2 = {

			/*

			 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for

			 * I2CHS IP's do not follow the usual pattern.

			 * prcm_reg_id alone cannot be used to program

			 * the iclk and fclk. Needs to be handled using

			 * additonal flags when clk handling is moved

			 * to hwmod framework.

			 */

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP2430_EN_I2CHS1_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,

		},

	},

	.slaves		= omap2430_i2c1_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2430_i2c1_slaves),

	.class		= &i2c_class,

	.dev_attr	= &i2c1_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),

};



/* I2C2 */



static struct omap_i2c_dev_attr i2c2_dev_attr = {

	.fifo_depth	= 8, /* bytes */

};



static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {

	{ .irq = INT_24XX_I2C2_IRQ, },

};



static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {

	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },

	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },

};



static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {

	&omap2430_l4_core__i2c2,

};



static struct omap_hwmod omap2430_i2c2_hwmod = {

	.name		= "i2c2",

	.mpu_irqs	= i2c2_mpu_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(i2c2_mpu_irqs),

	.sdma_reqs	= i2c2_sdma_reqs,

	.sdma_reqs_cnt	= ARRAY_SIZE(i2c2_sdma_reqs),

	.main_clk	= "i2chs2_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP2430_EN_I2CHS2_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,

		},

	},

	.slaves		= omap2430_i2c2_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap2430_i2c2_slaves),

	.class		= &i2c_class,

	.dev_attr	= &i2c2_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),

};



static __initdata struct omap_hwmod *omap2430_hwmods[] = {

	&omap2430_l3_main_hwmod,

	&omap2430_l4_core_hwmod,
@@ -428,6 +579,8 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { 
	&omap2430_uart1_hwmod,

	&omap2430_uart2_hwmod,

	&omap2430_uart3_hwmod,

	&omap2430_i2c1_hwmod,

	&omap2430_i2c2_hwmod,

	NULL,

};
@@ -435,5 +588,3 @@ int __init omap2430_hwmod_init(void) 
{

	return omap_hwmod_init(omap2430_hwmods);

}

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

+233 −0
Original line number Diff line number Diff line
@@ -18,6 +18,9 @@ 
#include <plat/cpu.h>

#include <plat/dma.h>

#include <plat/serial.h>

#include <plat/l4_3xxx.h>

#include <plat/i2c.h>

#include <plat/omap34xx.h>



#include "omap_hwmod_common_data.h"
@@ -39,6 +42,9 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod; 
static struct omap_hwmod omap3xxx_l4_core_hwmod;

static struct omap_hwmod omap3xxx_l4_per_hwmod;

static struct omap_hwmod omap3xxx_wd_timer2_hwmod;

static struct omap_hwmod omap3xxx_i2c1_hwmod;

static struct omap_hwmod omap3xxx_i2c2_hwmod;

static struct omap_hwmod omap3xxx_i2c3_hwmod;



/* L3 -> L4_CORE interface */

static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -169,6 +175,84 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { 
	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* I2C IP block address space length (in bytes) */

#define OMAP2_I2C_AS_LEN		128



/* L4 CORE -> I2C1 interface */

static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {

	{

		.pa_start	= 0x48070000,

		.pa_end		= 0x48070000 + OMAP2_I2C_AS_LEN - 1,

		.flags		= ADDR_TYPE_RT,

	},

};



static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {

	.master		= &omap3xxx_l4_core_hwmod,

	.slave		= &omap3xxx_i2c1_hwmod,

	.clk		= "i2c1_ick",

	.addr		= omap3xxx_i2c1_addr_space,

	.addr_cnt	= ARRAY_SIZE(omap3xxx_i2c1_addr_space),

	.fw = {

		.omap2 = {

			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,

			.l4_prot_group = 7,

			.flags	= OMAP_FIREWALL_L4,

		}

	},

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* L4 CORE -> I2C2 interface */

static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {

	{

		.pa_start	= 0x48072000,

		.pa_end		= 0x48072000 + OMAP2_I2C_AS_LEN - 1,

		.flags		= ADDR_TYPE_RT,

	},

};



static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {

	.master		= &omap3xxx_l4_core_hwmod,

	.slave		= &omap3xxx_i2c2_hwmod,

	.clk		= "i2c2_ick",

	.addr		= omap3xxx_i2c2_addr_space,

	.addr_cnt	= ARRAY_SIZE(omap3xxx_i2c2_addr_space),

	.fw = {

		.omap2 = {

			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,

			.l4_prot_group = 7,

			.flags = OMAP_FIREWALL_L4,

		}

	},

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* L4 CORE -> I2C3 interface */

static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {

	{

		.pa_start	= 0x48060000,

		.pa_end		= 0x48060000 + OMAP2_I2C_AS_LEN - 1,

		.flags		= ADDR_TYPE_RT,

	},

};



static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {

	.master		= &omap3xxx_l4_core_hwmod,

	.slave		= &omap3xxx_i2c3_hwmod,

	.clk		= "i2c3_ick",

	.addr		= omap3xxx_i2c3_addr_space,

	.addr_cnt	= ARRAY_SIZE(omap3xxx_i2c3_addr_space),

	.fw = {

		.omap2 = {

			.l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,

			.l4_prot_group = 7,

			.flags = OMAP_FIREWALL_L4,

		}

	},

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* Slave interfaces on the L4_CORE interconnect */

static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {

	&omap3xxx_l3_main__l4_core,
@@ -179,6 +263,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { 
	&omap3xxx_l4_core__l4_wkup,

	&omap3_l4_core__uart1,

	&omap3_l4_core__uart2,

	&omap3_l4_core__i2c1,

	&omap3_l4_core__i2c2,

	&omap3_l4_core__i2c3,

};



/* L4 CORE */
@@ -315,6 +402,18 @@ static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { 
	.sysc_fields    = &omap_hwmod_sysc_type1,

};



/* I2C common */

static struct omap_hwmod_class_sysconfig i2c_sysc = {

	.rev_offs	= 0x00,

	.sysc_offs	= 0x20,

	.syss_offs	= 0x10,

	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_AUTOIDLE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields    = &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {

	.name = "wd_timer",

	.sysc = &omap3xxx_wd_timer_sysc,
@@ -509,6 +608,137 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = { 
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),

};



static struct omap_hwmod_class i2c_class = {

	.name = "i2c",

	.sysc = &i2c_sysc,

};



/* I2C1 */



static struct omap_i2c_dev_attr i2c1_dev_attr = {

	.fifo_depth	= 8, /* bytes */

};



static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {

	{ .irq = INT_24XX_I2C1_IRQ, },

};



static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {

	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },

	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },

};



static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {

	&omap3_l4_core__i2c1,

};



static struct omap_hwmod omap3xxx_i2c1_hwmod = {

	.name		= "i2c1",

	.mpu_irqs	= i2c1_mpu_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(i2c1_mpu_irqs),

	.sdma_reqs	= i2c1_sdma_reqs,

	.sdma_reqs_cnt	= ARRAY_SIZE(i2c1_sdma_reqs),

	.main_clk	= "i2c1_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP3430_EN_I2C1_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,

		},

	},

	.slaves		= omap3xxx_i2c1_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap3xxx_i2c1_slaves),

	.class		= &i2c_class,

	.dev_attr	= &i2c1_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),

};



/* I2C2 */



static struct omap_i2c_dev_attr i2c2_dev_attr = {

	.fifo_depth	= 8, /* bytes */

};



static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {

	{ .irq = INT_24XX_I2C2_IRQ, },

};



static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {

	{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },

	{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },

};



static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {

	&omap3_l4_core__i2c2,

};



static struct omap_hwmod omap3xxx_i2c2_hwmod = {

	.name		= "i2c2",

	.mpu_irqs	= i2c2_mpu_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(i2c2_mpu_irqs),

	.sdma_reqs	= i2c2_sdma_reqs,

	.sdma_reqs_cnt	= ARRAY_SIZE(i2c2_sdma_reqs),

	.main_clk	= "i2c2_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP3430_EN_I2C2_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,

		},

	},

	.slaves		= omap3xxx_i2c2_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap3xxx_i2c2_slaves),

	.class		= &i2c_class,

	.dev_attr	= &i2c2_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),

};



/* I2C3 */



static struct omap_i2c_dev_attr i2c3_dev_attr = {

	.fifo_depth	= 64, /* bytes */

};



static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {

	{ .irq = INT_34XX_I2C3_IRQ, },

};



static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {

	{ .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },

	{ .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },

};



static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {

	&omap3_l4_core__i2c3,

};



static struct omap_hwmod omap3xxx_i2c3_hwmod = {

	.name		= "i2c3",

	.mpu_irqs	= i2c3_mpu_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(i2c3_mpu_irqs),

	.sdma_reqs	= i2c3_sdma_reqs,

	.sdma_reqs_cnt	= ARRAY_SIZE(i2c3_sdma_reqs),

	.main_clk	= "i2c3_fck",

	.prcm		= {

		.omap2 = {

			.module_offs = CORE_MOD,

			.prcm_reg_id = 1,

			.module_bit = OMAP3430_EN_I2C3_SHIFT,

			.idlest_reg_id = 1,

			.idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,

		},

	},

	.slaves		= omap3xxx_i2c3_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap3xxx_i2c3_slaves),

	.class		= &i2c_class,

	.dev_attr	= &i2c3_dev_attr,

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),

};



static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {

	&omap3xxx_l3_main_hwmod,

	&omap3xxx_l4_core_hwmod,
@@ -521,6 +751,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 
	&omap3xxx_uart2_hwmod,

	&omap3xxx_uart3_hwmod,

	&omap3xxx_uart4_hwmod,

	&omap3xxx_i2c1_hwmod,

	&omap3xxx_i2c2_hwmod,

	&omap3xxx_i2c3_hwmod,

	NULL,

};

arch/arm/mach-omap2/omap_hwmod_44xx_data.c

+237 −0
Original line number Diff line number Diff line
@@ -382,6 +382,238 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { 
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),

};



/*

 * 'i2c' class

 * multimaster high-speed i2c controller

 */



static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {

	.sysc_offs	= 0x0010,

	.syss_offs	= 0x0090,

	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |

			   SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |

			   SYSC_HAS_AUTOIDLE),

	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

	.sysc_fields	= &omap_hwmod_sysc_type1,

};



static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {

	.name = "i2c",

	.sysc = &omap44xx_i2c_sysc,

};



/* i2c1 */

static struct omap_hwmod omap44xx_i2c1_hwmod;

static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {

	{ .irq = 56 + OMAP44XX_IRQ_GIC_START },

};



static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {

	{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },

	{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },

};



static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {

	{

		.pa_start	= 0x48070000,

		.pa_end		= 0x480700ff,

		.flags		= ADDR_TYPE_RT

	},

};



/* l4_per -> i2c1 */

static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {

	.master		= &omap44xx_l4_per_hwmod,

	.slave		= &omap44xx_i2c1_hwmod,

	.clk		= "l4_div_ck",

	.addr		= omap44xx_i2c1_addrs,

	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c1_addrs),

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* i2c1 slave ports */

static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {

	&omap44xx_l4_per__i2c1,

};



static struct omap_hwmod omap44xx_i2c1_hwmod = {

	.name		= "i2c1",

	.class		= &omap44xx_i2c_hwmod_class,

	.flags		= HWMOD_INIT_NO_RESET,

	.mpu_irqs	= omap44xx_i2c1_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_irqs),

	.sdma_reqs	= omap44xx_i2c1_sdma_reqs,

	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),

	.main_clk	= "i2c1_fck",

	.prcm = {

		.omap4 = {

			.clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,

		},

	},

	.slaves		= omap44xx_i2c1_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c1_slaves),

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),

};



/* i2c2 */

static struct omap_hwmod omap44xx_i2c2_hwmod;

static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {

	{ .irq = 57 + OMAP44XX_IRQ_GIC_START },

};



static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {

	{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },

	{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },

};



static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {

	{

		.pa_start	= 0x48072000,

		.pa_end		= 0x480720ff,

		.flags		= ADDR_TYPE_RT

	},

};



/* l4_per -> i2c2 */

static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {

	.master		= &omap44xx_l4_per_hwmod,

	.slave		= &omap44xx_i2c2_hwmod,

	.clk		= "l4_div_ck",

	.addr		= omap44xx_i2c2_addrs,

	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c2_addrs),

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* i2c2 slave ports */

static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {

	&omap44xx_l4_per__i2c2,

};



static struct omap_hwmod omap44xx_i2c2_hwmod = {

	.name		= "i2c2",

	.class		= &omap44xx_i2c_hwmod_class,

	.flags		= HWMOD_INIT_NO_RESET,

	.mpu_irqs	= omap44xx_i2c2_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_irqs),

	.sdma_reqs	= omap44xx_i2c2_sdma_reqs,

	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),

	.main_clk	= "i2c2_fck",

	.prcm = {

		.omap4 = {

			.clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,

		},

	},

	.slaves		= omap44xx_i2c2_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c2_slaves),

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),

};



/* i2c3 */

static struct omap_hwmod omap44xx_i2c3_hwmod;

static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {

	{ .irq = 61 + OMAP44XX_IRQ_GIC_START },

};



static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {

	{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },

	{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },

};



static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {

	{

		.pa_start	= 0x48060000,

		.pa_end		= 0x480600ff,

		.flags		= ADDR_TYPE_RT

	},

};



/* l4_per -> i2c3 */

static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {

	.master		= &omap44xx_l4_per_hwmod,

	.slave		= &omap44xx_i2c3_hwmod,

	.clk		= "l4_div_ck",

	.addr		= omap44xx_i2c3_addrs,

	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c3_addrs),

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* i2c3 slave ports */

static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {

	&omap44xx_l4_per__i2c3,

};



static struct omap_hwmod omap44xx_i2c3_hwmod = {

	.name		= "i2c3",

	.class		= &omap44xx_i2c_hwmod_class,

	.flags		= HWMOD_INIT_NO_RESET,

	.mpu_irqs	= omap44xx_i2c3_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c3_irqs),

	.sdma_reqs	= omap44xx_i2c3_sdma_reqs,

	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),

	.main_clk	= "i2c3_fck",

	.prcm = {

		.omap4 = {

			.clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,

		},

	},

	.slaves		= omap44xx_i2c3_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c3_slaves),

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),

};



/* i2c4 */

static struct omap_hwmod omap44xx_i2c4_hwmod;

static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {

	{ .irq = 62 + OMAP44XX_IRQ_GIC_START },

};



static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {

	{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },

	{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },

};



static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {

	{

		.pa_start	= 0x48350000,

		.pa_end		= 0x483500ff,

		.flags		= ADDR_TYPE_RT

	},

};



/* l4_per -> i2c4 */

static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {

	.master		= &omap44xx_l4_per_hwmod,

	.slave		= &omap44xx_i2c4_hwmod,

	.clk		= "l4_div_ck",

	.addr		= omap44xx_i2c4_addrs,

	.addr_cnt	= ARRAY_SIZE(omap44xx_i2c4_addrs),

	.user		= OCP_USER_MPU | OCP_USER_SDMA,

};



/* i2c4 slave ports */

static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {

	&omap44xx_l4_per__i2c4,

};



static struct omap_hwmod omap44xx_i2c4_hwmod = {

	.name		= "i2c4",

	.class		= &omap44xx_i2c_hwmod_class,

	.flags		= HWMOD_INIT_NO_RESET,

	.mpu_irqs	= omap44xx_i2c4_irqs,

	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_i2c4_irqs),

	.sdma_reqs	= omap44xx_i2c4_sdma_reqs,

	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),

	.main_clk	= "i2c4_fck",

	.prcm = {

		.omap4 = {

			.clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,

		},

	},

	.slaves		= omap44xx_i2c4_slaves,

	.slaves_cnt	= ARRAY_SIZE(omap44xx_i2c4_slaves),

	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),

};



/*

 * 'mpu_bus' class

 * instance(s): mpu_private
@@ -826,6 +1058,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { 
	&omap44xx_l4_cfg_hwmod,

	&omap44xx_l4_per_hwmod,

	&omap44xx_l4_wkup_hwmod,

	/* i2c class */

	&omap44xx_i2c1_hwmod,

	&omap44xx_i2c2_hwmod,

	&omap44xx_i2c3_hwmod,

	&omap44xx_i2c4_hwmod,

	/* mpu_bus class */

	&omap44xx_mpu_private_hwmod,