Loading arch/arm/boot/dts/qcom/mdm9640.dtsi +20 −12 Original line number Diff line number Diff line Loading @@ -625,16 +625,19 @@ ranges; interrupt-parent = <&usb3>; interrupts = <0 1 2>; interrupts = <0 1 2 3>; #interrupt-cells = <1>; interrupt-map-mask = <0x0 0xffffffff>; interrupt-map = <0x0 0 &intc 0 202 0 0x0 1 &intc 0 180 0 0x0 2 &spmi_bus 0x0 0x0 0xc3 0x0>; interrupt-names = "hs_phy_irq", "pwr_event_irq", 0x0 1 &intc 0 203 0 0x0 2 &intc 0 180 0 0x0 3 &spmi_bus 0x0 0x0 0xc3 0x0>; interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq", "pmic_id_irq"; qcom,otg-capability; USB3_GDSC-supply = <&gdsc_usb30>; vdda33-supply = <&pmd9635_l10>; vdda18-supply = <&pmd9635_l8>; qcom,usb-dbm = <&dbm_1p5>; qcom,msm-bus,name = "usb3"; Loading @@ -659,14 +662,14 @@ compatible = "synopsys,dwc3"; reg = <0x08a00000 0xf8000>; interrupt-parent = <&intc>; interrupts = <0 131 0>; interrupts = <0 131 0>, <0 134 0>; interrupt-names = "irq", "otg_irq"; usb-phy = <&qusb_phy>, <&ssphy>; snps,nominal-elastic-buffer; snps,hsphy-auto-suspend-disable; snps,ssphy-auto-suspend-disable; snps,has-lpm-erratum; snps,lpm-nyet-threshold = /bits/ 8 <0x8>; snps,hird-threshold = /bits/ 8 <0x7>; snps,hird_thresh = <0x7>; snps,lpm-nyet-thresh = <0x8>; snps,bus-suspend-enable; snps,usb3-u1u2-disable; }; Loading @@ -674,6 +677,7 @@ qcom,usbbam@8b04000 { compatible = "qcom,usb-bam-msm"; reg = <0x08b04000 0x1b000>; interrupt-parent = <&intc>; interrupts = <0 132 0>; qcom,bam-type = <0>; Loading Loading @@ -812,8 +816,10 @@ ssphy: ssphy@78000 { compatible = "qcom,usb-ssphy-qmp-v1"; reg = <0x00078000 0x750>, <0x0007e000 0x400>, <0x01947244 0x4>; reg-names = "qmp_phy_base", "qmp_ahb2phy_base", "vls_clamp_reg"; vdd-supply = <&pmd9635_l4>; vdda18-supply = <&pmd9635_l8>; Loading @@ -827,10 +833,12 @@ <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>, <&clock_gcc clk_gcc_usb3_phy_reset>, <&clock_gcc clk_gcc_usb3phy_phy_reset>, <&clock_gcc clk_ln_bb_clk>, <&clock_gcc clk_usb_ss_ldo>; clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset", "phy_phy_reset", "ldo_clk"; "phy_reset", "phy_phy_reset", "ref_clk_src", "ref_clk"; }; dbm_1p5: dbm@8af8000 { Loading Loading
arch/arm/boot/dts/qcom/mdm9640.dtsi +20 −12 Original line number Diff line number Diff line Loading @@ -625,16 +625,19 @@ ranges; interrupt-parent = <&usb3>; interrupts = <0 1 2>; interrupts = <0 1 2 3>; #interrupt-cells = <1>; interrupt-map-mask = <0x0 0xffffffff>; interrupt-map = <0x0 0 &intc 0 202 0 0x0 1 &intc 0 180 0 0x0 2 &spmi_bus 0x0 0x0 0xc3 0x0>; interrupt-names = "hs_phy_irq", "pwr_event_irq", 0x0 1 &intc 0 203 0 0x0 2 &intc 0 180 0 0x0 3 &spmi_bus 0x0 0x0 0xc3 0x0>; interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq", "pmic_id_irq"; qcom,otg-capability; USB3_GDSC-supply = <&gdsc_usb30>; vdda33-supply = <&pmd9635_l10>; vdda18-supply = <&pmd9635_l8>; qcom,usb-dbm = <&dbm_1p5>; qcom,msm-bus,name = "usb3"; Loading @@ -659,14 +662,14 @@ compatible = "synopsys,dwc3"; reg = <0x08a00000 0xf8000>; interrupt-parent = <&intc>; interrupts = <0 131 0>; interrupts = <0 131 0>, <0 134 0>; interrupt-names = "irq", "otg_irq"; usb-phy = <&qusb_phy>, <&ssphy>; snps,nominal-elastic-buffer; snps,hsphy-auto-suspend-disable; snps,ssphy-auto-suspend-disable; snps,has-lpm-erratum; snps,lpm-nyet-threshold = /bits/ 8 <0x8>; snps,hird-threshold = /bits/ 8 <0x7>; snps,hird_thresh = <0x7>; snps,lpm-nyet-thresh = <0x8>; snps,bus-suspend-enable; snps,usb3-u1u2-disable; }; Loading @@ -674,6 +677,7 @@ qcom,usbbam@8b04000 { compatible = "qcom,usb-bam-msm"; reg = <0x08b04000 0x1b000>; interrupt-parent = <&intc>; interrupts = <0 132 0>; qcom,bam-type = <0>; Loading Loading @@ -812,8 +816,10 @@ ssphy: ssphy@78000 { compatible = "qcom,usb-ssphy-qmp-v1"; reg = <0x00078000 0x750>, <0x0007e000 0x400>, <0x01947244 0x4>; reg-names = "qmp_phy_base", "qmp_ahb2phy_base", "vls_clamp_reg"; vdd-supply = <&pmd9635_l4>; vdda18-supply = <&pmd9635_l8>; Loading @@ -827,10 +833,12 @@ <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>, <&clock_gcc clk_gcc_usb3_phy_reset>, <&clock_gcc clk_gcc_usb3phy_phy_reset>, <&clock_gcc clk_ln_bb_clk>, <&clock_gcc clk_usb_ss_ldo>; clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset", "phy_phy_reset", "ldo_clk"; "phy_reset", "phy_phy_reset", "ref_clk_src", "ref_clk"; }; dbm_1p5: dbm@8af8000 { Loading