Merge branch for-rmk-devel of git://aeryn.fluff.org.uk/bjdooks/linux into devel

-----------

  Each pin has an unique number associated with it in regs-gpio.h,

  eg S3C2410_GPA0 or S3C2410_GPF1. These defines are used to tell

  eg S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell

  the GPIO functions which pin is to be used.

  Eg:

     s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);

     s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);

     s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0);

     s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);

   which would turn GPA0 into the lowest Address line A0, and set

   GPE8 to be connected to the SDIO/MMC controller's SDDAT1 line.

   which would turn GPA(0) into the lowest Address line A0, and set

   GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line.

Reading the current configuration

config ARM_VIC

	bool

config ARM_VIC_NR

	int

	default 2

	help

	  The maximum number of VICs available in the system, for

	  power management.

config ICST525

	bool

#include <linux/init.h>

#include <linux/list.h>

#include <linux/io.h>

#include <linux/sysdev.h>

#include <asm/mach/irq.h>

#include <asm/hardware/vic.h>

	writel(1 << irq, base + VIC_INT_ENABLE);

}

/**

 * vic_init2 - common initialisation code

 * @base: Base of the VIC.

 *

 * Common initialisation code for registeration

 * and resume.

*/

static void vic_init2(void __iomem *base)

{

	int i;

	for (i = 0; i < 16; i++) {

		void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);

		writel(VIC_VECT_CNTL_ENABLE | i, reg);

	}

	writel(32, base + VIC_PL190_DEF_VECT_ADDR);

}

#if defined(CONFIG_PM)

/**

 * struct vic_device - VIC PM device

 * @sysdev: The system device which is registered.

 * @irq: The IRQ number for the base of the VIC.

 * @base: The register base for the VIC.

 * @resume_sources: A bitmask of interrupts for resume.

 * @resume_irqs: The IRQs enabled for resume.

 * @int_select: Save for VIC_INT_SELECT.

 * @int_enable: Save for VIC_INT_ENABLE.

 * @soft_int: Save for VIC_INT_SOFT.

 * @protect: Save for VIC_PROTECT.

 */

struct vic_device {

	struct sys_device sysdev;

	void __iomem	*base;

	int		irq;

	u32		resume_sources;

	u32		resume_irqs;

	u32		int_select;

	u32		int_enable;

	u32		soft_int;

	u32		protect;

};

/* we cannot allocate memory when VICs are initially registered */

static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];

static inline struct vic_device *to_vic(struct sys_device *sys)

{

	return container_of(sys, struct vic_device, sysdev);

}

static int vic_id;

static int vic_class_resume(struct sys_device *dev)

{

	struct vic_device *vic = to_vic(dev);

	void __iomem *base = vic->base;

	printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);

	/* re-initialise static settings */

	vic_init2(base);

	writel(vic->int_select, base + VIC_INT_SELECT);

	writel(vic->protect, base + VIC_PROTECT);

	/* set the enabled ints and then clear the non-enabled */

	writel(vic->int_enable, base + VIC_INT_ENABLE);

	writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);

	/* and the same for the soft-int register */

	writel(vic->soft_int, base + VIC_INT_SOFT);

	writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);

	return 0;

}

static int vic_class_suspend(struct sys_device *dev, pm_message_t state)

{

	struct vic_device *vic = to_vic(dev);

	void __iomem *base = vic->base;

	printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);

	vic->int_select = readl(base + VIC_INT_SELECT);

	vic->int_enable = readl(base + VIC_INT_ENABLE);

	vic->soft_int = readl(base + VIC_INT_SOFT);

	vic->protect = readl(base + VIC_PROTECT);

	/* set the interrupts (if any) that are used for

	 * resuming the system */

	writel(vic->resume_irqs, base + VIC_INT_ENABLE);

	writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);

	return 0;

}

struct sysdev_class vic_class = {

	.name		= "vic",

	.suspend	= vic_class_suspend,

	.resume		= vic_class_resume,

};

/**

 * vic_pm_register - Register a VIC for later power management control

 * @base: The base address of the VIC.

 * @irq: The base IRQ for the VIC.

 * @resume_sources: bitmask of interrupts allowed for resume sources.

 *

 * Register the VIC with the system device tree so that it can be notified

 * of suspend and resume requests and ensure that the correct actions are

 * taken to re-instate the settings on resume.

 */

static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)

{

	struct vic_device *v;

	if (vic_id >= ARRAY_SIZE(vic_devices))

		printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);

	else {

		v = &vic_devices[vic_id];

		v->base = base;

		v->resume_sources = resume_sources;

		v->irq = irq;

		vic_id++;

	}

}

/**

 * vic_pm_init - initicall to register VIC pm

 *

 * This is called via late_initcall() to register

 * the resources for the VICs due to the early

 * nature of the VIC's registration.

*/

static int __init vic_pm_init(void)

{

	struct vic_device *dev = vic_devices;

	int err;

	int id;

	if (vic_id == 0)

		return 0;

	err = sysdev_class_register(&vic_class);

	if (err) {

		printk(KERN_ERR "%s: cannot register class\n", __func__);

		return err;

	}

	for (id = 0; id < vic_id; id++, dev++) {

		dev->sysdev.id = id;

		dev->sysdev.cls = &vic_class;

		err = sysdev_register(&dev->sysdev);

		if (err) {

			printk(KERN_ERR "%s: failed to register device\n",

			       __func__);

			return err;

		}

	}

	return 0;

}

late_initcall(vic_pm_init);

static struct vic_device *vic_from_irq(unsigned int irq)

{

        struct vic_device *v = vic_devices;

	unsigned int base_irq = irq & ~31;

	int id;

	for (id = 0; id < vic_id; id++, v++) {

		if (v->irq == base_irq)

			return v;

	}

	return NULL;

}

static int vic_set_wake(unsigned int irq, unsigned int on)

{

	struct vic_device *v = vic_from_irq(irq);

	unsigned int off = irq & 31;

	if (!v)

		return -EINVAL;

	if (on)

		v->resume_irqs |= 1 << off;

	else

		v->resume_irqs &= ~(1 << off);

	return 0;

}

#else

static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }

#define vic_set_wake NULL

#endif /* CONFIG_PM */

static struct irq_chip vic_chip = {

	.name	= "VIC",

	.ack	= vic_mask_irq,

	.mask	= vic_mask_irq,

	.unmask	= vic_unmask_irq,

	.set_wake = vic_set_wake,

};

/**

 * @base: iomem base address

 * @irq_start: starting interrupt number, must be muliple of 32

 * @vic_sources: bitmask of interrupt sources to allow

 * @resume_sources: bitmask of interrupt sources to allow for resume

 */

void __init vic_init(void __iomem *base, unsigned int irq_start,

		     u32 vic_sources)

		     u32 vic_sources, u32 resume_sources)

{

	unsigned int i;

		writel(value, base + VIC_PL190_VECT_ADDR);

	}

	for (i = 0; i < 16; i++) {

		void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);

		writel(VIC_VECT_CNTL_ENABLE | i, reg);

	}

	writel(32, base + VIC_PL190_DEF_VECT_ADDR);

	vic_init2(base);

	for (i = 0; i < 32; i++) {

		if (vic_sources & (1 << i)) {

			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);

		}

	}

	vic_pm_register(base, irq_start, resume_sources);

}

/* arch/arm/include/asm/hardware/pl080.h

 *

 * Copyright 2008 Openmoko, Inc.

 * Copyright 2008 Simtec Electronics

 *      http://armlinux.simtec.co.uk/

 *      Ben Dooks <ben@simtec.co.uk>

 *

 * ARM PrimeCell PL080 DMA controller

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/

/* Note, there are some Samsung updates to this controller block which

 * make it not entierly compatible with the PL080 specification from

 * ARM. When in doubt, check the Samsung documentation first.

 *

 * The Samsung defines are PL080S, and add an extra controll register,

 * the ability to move more than 2^11 counts of data and some extra

 * OneNAND features.

*/

#define PL080_INT_STATUS			(0x00)

#define PL080_TC_STATUS				(0x04)

#define PL080_TC_CLEAR				(0x08)

#define PL080_ERR_STATUS			(0x0C)

#define PL080_ERR_CLEAR				(0x10)

#define PL080_RAW_TC_STATUS			(0x14)

#define PL080_RAW_ERR_STATUS			(0x18)

#define PL080_EN_CHAN				(0x1c)

#define PL080_SOFT_BREQ				(0x20)

#define PL080_SOFT_SREQ				(0x24)

#define PL080_SOFT_LBREQ			(0x28)

#define PL080_SOFT_LSREQ			(0x2C)

#define PL080_CONFIG				(0x30)

#define PL080_CONFIG_M2_BE			(1 << 2)

#define PL080_CONFIG_M1_BE			(1 << 1)

#define PL080_CONFIG_ENABLE			(1 << 0)

#define PL080_SYNC				(0x34)

/* Per channel configuration registers */

#define PL008_Cx_STRIDE				(0x20)

#define PL080_Cx_BASE(x)			((0x100 + (x * 0x20)))

#define PL080_Cx_SRC_ADDR(x)			((0x100 + (x * 0x20)))

#define PL080_Cx_DST_ADDR(x)			((0x104 + (x * 0x20)))

#define PL080_Cx_LLI(x)				((0x108 + (x * 0x20)))

#define PL080_Cx_CONTROL(x)			((0x10C + (x * 0x20)))

#define PL080_Cx_CONFIG(x)			((0x110 + (x * 0x20)))

#define PL080S_Cx_CONTROL2(x)			((0x110 + (x * 0x20)))

#define PL080S_Cx_CONFIG(x)			((0x114 + (x * 0x20)))

#define PL080_CH_SRC_ADDR			(0x00)

#define PL080_CH_DST_ADDR			(0x04)

#define PL080_CH_LLI				(0x08)

#define PL080_CH_CONTROL			(0x0C)

#define PL080_CH_CONFIG				(0x10)

#define PL080S_CH_CONTROL2			(0x10)

#define PL080S_CH_CONFIG			(0x14)

#define PL080_LLI_ADDR_MASK			(0x3fffffff << 2)

#define PL080_LLI_ADDR_SHIFT			(2)

#define PL080_LLI_LM_AHB2			(1 << 0)

#define PL080_CONTROL_TC_IRQ_EN			(1 << 31)

#define PL080_CONTROL_PROT_MASK			(0x7 << 28)

#define PL080_CONTROL_PROT_SHIFT		(28)

#define PL080_CONTROL_PROT_SYS			(1 << 28)

#define PL080_CONTROL_DST_INCR			(1 << 27)

#define PL080_CONTROL_SRC_INCR			(1 << 26)

#define PL080_CONTROL_DST_AHB2			(1 << 25)

#define PL080_CONTROL_SRC_AHB2			(1 << 24)

#define PL080_CONTROL_DWIDTH_MASK		(0x7 << 21)

#define PL080_CONTROL_DWIDTH_SHIFT		(21)

#define PL080_CONTROL_SWIDTH_MASK		(0x7 << 18)

#define PL080_CONTROL_SWIDTH_SHIFT		(18)

#define PL080_CONTROL_DB_SIZE_MASK		(0x7 << 15)

#define PL080_CONTROL_DB_SIZE_SHIFT		(15)

#define PL080_CONTROL_SB_SIZE_MASK		(0x7 << 12)

#define PL080_CONTROL_SB_SIZE_SHIFT		(12)

#define PL080_CONTROL_TRANSFER_SIZE_MASK	(0xfff << 0)

#define PL080_CONTROL_TRANSFER_SIZE_SHIFT	(0)

#define PL080_BSIZE_1				(0x0)

#define PL080_BSIZE_4				(0x1)

#define PL080_BSIZE_8				(0x2)

#define PL080_BSIZE_16				(0x3)

#define PL080_BSIZE_32				(0x4)

#define PL080_BSIZE_64				(0x5)

#define PL080_BSIZE_128				(0x6)

#define PL080_BSIZE_256				(0x7)

#define PL080_WIDTH_8BIT			(0x0)

#define PL080_WIDTH_16BIT			(0x1)

#define PL080_WIDTH_32BIT			(0x2)

#define PL080_CONFIG_HALT			(1 << 18)

#define PL080_CONFIG_ACTIVE			(1 << 17)  /* RO */

#define PL080_CONFIG_LOCK			(1 << 16)

#define PL080_CONFIG_TC_IRQ_MASK		(1 << 15)

#define PL080_CONFIG_ERR_IRQ_MASK		(1 << 14)

#define PL080_CONFIG_FLOW_CONTROL_MASK		(0x7 << 11)

#define PL080_CONFIG_FLOW_CONTROL_SHIFT		(11)

#define PL080_CONFIG_DST_SEL_MASK		(0xf << 6)

#define PL080_CONFIG_DST_SEL_SHIFT		(6)

#define PL080_CONFIG_SRC_SEL_MASK		(0xf << 1)

#define PL080_CONFIG_SRC_SEL_SHIFT		(1)

#define PL080_CONFIG_ENABLE			(1 << 0)

#define PL080_FLOW_MEM2MEM			(0x0)

#define PL080_FLOW_MEM2PER			(0x1)

#define PL080_FLOW_PER2MEM			(0x2)

#define PL080_FLOW_SRC2DST			(0x3)

#define PL080_FLOW_SRC2DST_DST			(0x4)

#define PL080_FLOW_MEM2PER_PER			(0x5)

#define PL080_FLOW_PER2MEM_PER			(0x6)

#define PL080_FLOW_SRC2DST_SRC			(0x7)

/* DMA linked list chain structure */

struct pl080_lli {

	u32	src_addr;

	u32	dst_addr;

	u32	next_lli;

	u32	control0;

};

struct pl080s_lli {

	u32	src_addr;

	u32	dst_addr;

	u32	next_lli;

	u32	control0;

	u32	control1;

};

#define VIC_PL192_VECT_ADDR		0xF00

#ifndef __ASSEMBLY__

void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);

void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);

#endif

#endif