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Commit 54259738 authored by Digish Pandya's avatar Digish Pandya
Browse files

msm: kgsl: Add support for A306A GPU 



Add new GPU ID, macros and VBIF settings for
new GPU revision A306A.

Change-Id: Iddc624c4aa89e741c28d0ab2534d36097ed19525
Signed-off-by: default avatarDigish Pandya <digishp@codeaurora.org>
parent f81d0b1f

drivers/gpu/msm/a3xx_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -861,6 +861,7 @@ 
#define A305_RBBM_CLOCK_CTL_DEFAULT   0xAAAAAAAA

#define A305C_RBBM_CLOCK_CTL_DEFAULT  0xAAAAAAAA

#define A306_RBBM_CLOCK_CTL_DEFAULT   0xAAAAAAAA

#define A306A_RBBM_CLOCK_CTL_DEFAULT  0xAAAAAAAA

#define A310_RBBM_CLOCK_CTL_DEFAULT   0xAAAAAAAA

#define A320_RBBM_CLOCK_CTL_DEFAULT   0xBFFFFFFF

#define A330_RBBM_CLOCK_CTL_DEFAULT   0xBFFCFFFF

drivers/gpu/msm/adreno-gpulist.h

+12 −0
Original line number Diff line number Diff line
@@ -26,6 +26,18 @@ static const struct adreno_gpu_core adreno_gpulist[] = { 
		.gmem_size = SZ_128K,

		.busy_mask = 0x7FFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A306A,

		.core = 3,

		.major = 0,

		.minor = 6,

		.patchid = 0x20,

		.pm4fw_name = "a300_pm4.fw",

		.pfpfw_name = "a300_pfp.fw",

		.gpudev = &adreno_a3xx_gpudev,

		.gmem_size = SZ_128K,

		.busy_mask = 0x7FFFFFFE,

	},

	{

		.gpurev = ADRENO_REV_A304,

		.core = 3,

drivers/gpu/msm/adreno.h

+2 −0
Original line number Diff line number Diff line
@@ -144,6 +144,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A305 = 305,

	ADRENO_REV_A305C = 306,

	ADRENO_REV_A306 = 307,

	ADRENO_REV_A306A = 308,

	ADRENO_REV_A310 = 310,

	ADRENO_REV_A320 = 320,

	ADRENO_REV_A330 = 330,
@@ -885,6 +886,7 @@ ADRENO_TARGET(a305, ADRENO_REV_A305) 
ADRENO_TARGET(a305b, ADRENO_REV_A305B)

ADRENO_TARGET(a305c, ADRENO_REV_A305C)

ADRENO_TARGET(a306, ADRENO_REV_A306)

ADRENO_TARGET(a306a, ADRENO_REV_A306A)

ADRENO_TARGET(a310, ADRENO_REV_A310)

ADRENO_TARGET(a320, ADRENO_REV_A320)

ADRENO_TARGET(a330, ADRENO_REV_A330)

drivers/gpu/msm/adreno_a3xx.c

+13 −2
Original line number Diff line number Diff line
@@ -120,6 +120,8 @@ unsigned int adreno_a3xx_rbbm_clock_ctl_default(struct adreno_device 
		return A305C_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a306(adreno_dev))

		return A306_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a306a(adreno_dev))

		return A306A_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a310(adreno_dev))

		return A310_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a320(adreno_dev))
@@ -611,7 +613,7 @@ static void a3xx_platform_setup(struct adreno_device *adreno_dev) 
	struct adreno_gpudev *gpudev;

	const struct adreno_reg_offsets *reg_offsets;



	if (adreno_is_a306(adreno_dev)) {

	if (adreno_is_a306(adreno_dev) || adreno_is_a306a(adreno_dev)) {

		gpudev = ADRENO_GPU_DEVICE(adreno_dev);

		reg_offsets = gpudev->reg_offsets;

		reg_offsets->offsets[ADRENO_REG_VBIF_XIN_HALT_CTRL0] =
@@ -847,6 +849,13 @@ static const struct adreno_vbif_data a306_vbif[] = { 
	{0, 0},

};



static const struct adreno_vbif_data a306a_vbif[] = {

	{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },

	{ A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000A },

	{ A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000A },

	{0, 0},

};



static const struct adreno_vbif_data a310_vbif[] = {

	{ A3XX_VBIF_ABIT_SORT, 0x0001000F },

	{ A3XX_VBIF_ABIT_SORT_CONF, 0x000000A4 },
@@ -943,6 +952,7 @@ static const struct adreno_vbif_platform a3xx_vbif_platforms[] = { 
	{ adreno_is_a305, a305_vbif },

	{ adreno_is_a305c, a305c_vbif },

	{ adreno_is_a306, a306_vbif },

	{ adreno_is_a306a, a306a_vbif },

	{ adreno_is_a310, a310_vbif },

	{ adreno_is_a320, a320_vbif },

	/* A330v2.1 needs to be ahead of A330v2 so the right device matches */
@@ -1189,7 +1199,8 @@ static void a3xx_perfcounter_init(struct adreno_device *adreno_dev) 
		a3xx_perfcounters_sp[3].countable = KGSL_PERFCOUNTER_BROKEN;



	if (counters &&

		(adreno_is_a306(adreno_dev) || adreno_is_a304(adreno_dev))) {

		(adreno_is_a306(adreno_dev) || adreno_is_a304(adreno_dev) ||

		adreno_is_a306a(adreno_dev))) {

		counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF].regs =

			a3xx_perfcounters_vbif2;

		counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF_PWR].regs =

drivers/gpu/msm/adreno_ringbuffer.c

+2 −1
Original line number Diff line number Diff line
@@ -297,7 +297,8 @@ static void _ringbuffer_setup_common(struct adreno_ringbuffer *rb) 


	/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */

	if (adreno_is_a305(adreno_dev) || adreno_is_a305c(adreno_dev) ||

		adreno_is_a306(adreno_dev) || adreno_is_a320(adreno_dev) ||

		adreno_is_a306(adreno_dev) || adreno_is_a306a(adreno_dev) ||

		adreno_is_a320(adreno_dev) ||

		adreno_is_a304(adreno_dev))

		kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x000E0602);

	else if (adreno_is_a330(adreno_dev) || adreno_is_a305b(adreno_dev) ||