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Commit 53ed1389 authored by Paul Burton's avatar Paul Burton
Browse files

MIPS: uasm: add wait instruction 



This patch allows use of the wait instruction from uasm. It will be used
by a subsequent patch.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
parent 729ff561

arch/mips/include/asm/uasm.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -147,6 +147,7 @@ Ip_0(_tlbp); 
Ip_0(_tlbr);

Ip_0(_tlbr);

Ip_0(_tlbwi);

Ip_0(_tlbwi);

Ip_0(_tlbwr);

Ip_0(_tlbwr);

Ip_u1(_wait);

Ip_u3u1u2(_xor);

Ip_u3u1u2(_xor);

Ip_u2u1u3(_xori);

Ip_u2u1u3(_xori);

arch/mips/mm/uasm-micromips.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -104,6 +104,7 @@ static struct insn insn_table_MM[] = { 
	{ insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 },

	{ insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 },

	{ insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 },

	{ insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 },

	{ insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 },

	{ insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 },

	{ insn_wait, M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM },

	{ insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD },

	{ insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD },

	{ insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },

	{ insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },

	{ insn_dins, 0, 0 },

	{ insn_dins, 0, 0 },

arch/mips/mm/uasm-mips.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -113,6 +113,7 @@ static struct insn insn_table[] = { 
	{ insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },

	{ insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },

	{ insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },

	{ insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },

	{ insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },

	{ insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },

	{ insn_wait, M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM },

	{ insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },

	{ insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },

	{ insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },

	{ insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },

	{ insn_invalid, 0, 0 }

	{ insn_invalid, 0, 0 }

arch/mips/mm/uasm.c

+2 −1
Original line number Original line Diff line number Diff line
@@ -54,7 +54,7 @@ enum opcode { 
	insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc,

	insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc,

	insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,

	insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,

	insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr,

	insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr,

	insn_xor, insn_xori,

	insn_wait, insn_xor, insn_xori,

};

};





struct insn {

struct insn {
@@ -276,6 +276,7 @@ I_0(_tlbp) 
I_0(_tlbr)

I_0(_tlbr)

I_0(_tlbwi)

I_0(_tlbwi)

I_0(_tlbwr)

I_0(_tlbwr)

I_u1(_wait);

I_u3u1u2(_xor)

I_u3u1u2(_xor)

I_u2u1u3(_xori)

I_u2u1u3(_xori)

I_u2u1msbu3(_dins);

I_u2u1msbu3(_dins);