Loading Documentation/devicetree/bindings/fb/mdss-mdp.txt +8 −0 Original line number Diff line number Diff line Loading @@ -93,6 +93,14 @@ Required properties to the respective cursor pipes. Number of xin ids defined should match the number of offsets defined in property: qcom,mdss-pipe-cursor-off - qcom,mdss-pipe-cursor-clk-ctrl-off: Array of offsets describing clk control offsets for dynamic clock gating. 1st value in the array represents offset of the control register. 2nd value represents bit offset within control register and 3rd value represents bit offset within status register. Number of tuples defined should match the number of offsets defined in property: qcom,mdss-pipe-cursor-off - qcom,mdss-ctl-off: Array of offset addresses for the available ctl hw blocks within MDP, these offsets are calculated from register "mdp_phys" defined in Loading arch/arm/boot/dts/qcom/msm8996-mdss.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,9 @@ <0x2C4 4 8>; qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>, <0x2B4 8 12>; qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>, <0x3B0 16 15>; qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400 0x00002600 0x00002800>; Loading drivers/video/msm/mdss/mdss_mdp.c +8 −1 Original line number Diff line number Diff line Loading @@ -2253,10 +2253,17 @@ static int mdss_mdp_parse_dt_pipe(struct platform_device *pdev) goto parse_fail; rc = mdss_mdp_parse_dt_handler(pdev, "qcom,mdss-pipe-dma-xin-id", xin_id, "qcom,mdss-pipe-cursor-xin-id", xin_id, mdata->ncursor_pipes); if (rc) goto parse_fail; rc = mdss_mdp_parse_dt_pipe_clk_ctrl(pdev, "qcom,mdss-pipe-cursor-clk-ctrl-offsets", mdata->cursor_pipes, mdata->ncursor_pipes); if (rc) goto parse_fail; /* set the fetch id to an invalid value */ for (i = 0; i < mdata->ncursor_pipes; i++) ftch_id[i] = -1; Loading drivers/video/msm/mdss/mdss_mdp_layer.c +3 −3 Original line number Diff line number Diff line Loading @@ -36,9 +36,9 @@ #define CHECK_LAYER_BOUNDS(offset, size, max_size) \ (((size) > (max_size)) || ((offset) > ((max_size) - (size)))) #define IS_PIPE_TYPE_CURSOR(pipe_id) \ ((pipe_id >= MDSS_MDP_SSPP_CURSOR0) &&\ (pipe_id <= MDSS_MDP_SSPP_CURSOR1)) #define IS_PIPE_TYPE_CURSOR(pipe_ndx) \ ((pipe_ndx >= (1 << MDSS_MDP_SSPP_CURSOR0)) &&\ (pipe_ndx <= (1 << MDSS_MDP_SSPP_CURSOR1))) enum { MDSS_MDP_RELEASE_FENCE = 0, Loading drivers/video/msm/mdss/mdss_mdp_pipe.c +14 −3 Original line number Diff line number Diff line Loading @@ -1312,8 +1312,8 @@ static int mdss_mdp_is_pipe_idle(struct mdss_mdp_pipe *pipe, reg_val = readl_relaxed(mdata->mdp_base + pipe->clk_status.reg_off); if (reg_val & clk_status_idle_mask) is_idle = false; if ((reg_val & clk_status_idle_mask) == 0) is_idle = true; pr_debug("pipe#:%d clk_status:0x%x clk_status_idle_mask:0x%x\n", pipe->num, reg_val, clk_status_idle_mask); Loading @@ -1322,13 +1322,24 @@ static int mdss_mdp_is_pipe_idle(struct mdss_mdp_pipe *pipe, if (!ignore_force_on && (is_forced_on || !is_idle)) goto exit; /* * skip vbif check for cursor pipes as the same xin-id is shared * between cursor0, cursor1 and dsi */ if (pipe->type == MDSS_MDP_PIPE_TYPE_CURSOR) { if (ignore_force_on && is_forced_on) is_idle = true; goto exit; } vbif_idle_mask = BIT(pipe->xin_id + 16); reg_val = MDSS_VBIF_READ(mdata, MMSS_VBIF_XIN_HALT_CTRL1, is_nrt_vbif); if (reg_val & vbif_idle_mask) is_idle = true; pr_debug("pipe#:%d XIN_HALT_CTRL1: 0x%x\n", pipe->num, reg_val); pr_debug("pipe#:%d XIN_HALT_CTRL1: 0x%x, vbif_idle_mask: 0x%x\n", pipe->num, reg_val, vbif_idle_mask); exit: mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF); Loading Loading
Documentation/devicetree/bindings/fb/mdss-mdp.txt +8 −0 Original line number Diff line number Diff line Loading @@ -93,6 +93,14 @@ Required properties to the respective cursor pipes. Number of xin ids defined should match the number of offsets defined in property: qcom,mdss-pipe-cursor-off - qcom,mdss-pipe-cursor-clk-ctrl-off: Array of offsets describing clk control offsets for dynamic clock gating. 1st value in the array represents offset of the control register. 2nd value represents bit offset within control register and 3rd value represents bit offset within status register. Number of tuples defined should match the number of offsets defined in property: qcom,mdss-pipe-cursor-off - qcom,mdss-ctl-off: Array of offset addresses for the available ctl hw blocks within MDP, these offsets are calculated from register "mdp_phys" defined in Loading
arch/arm/boot/dts/qcom/msm8996-mdss.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -79,6 +79,9 @@ <0x2C4 4 8>; qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>, <0x2B4 8 12>; qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>, <0x3B0 16 15>; qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400 0x00002600 0x00002800>; Loading
drivers/video/msm/mdss/mdss_mdp.c +8 −1 Original line number Diff line number Diff line Loading @@ -2253,10 +2253,17 @@ static int mdss_mdp_parse_dt_pipe(struct platform_device *pdev) goto parse_fail; rc = mdss_mdp_parse_dt_handler(pdev, "qcom,mdss-pipe-dma-xin-id", xin_id, "qcom,mdss-pipe-cursor-xin-id", xin_id, mdata->ncursor_pipes); if (rc) goto parse_fail; rc = mdss_mdp_parse_dt_pipe_clk_ctrl(pdev, "qcom,mdss-pipe-cursor-clk-ctrl-offsets", mdata->cursor_pipes, mdata->ncursor_pipes); if (rc) goto parse_fail; /* set the fetch id to an invalid value */ for (i = 0; i < mdata->ncursor_pipes; i++) ftch_id[i] = -1; Loading
drivers/video/msm/mdss/mdss_mdp_layer.c +3 −3 Original line number Diff line number Diff line Loading @@ -36,9 +36,9 @@ #define CHECK_LAYER_BOUNDS(offset, size, max_size) \ (((size) > (max_size)) || ((offset) > ((max_size) - (size)))) #define IS_PIPE_TYPE_CURSOR(pipe_id) \ ((pipe_id >= MDSS_MDP_SSPP_CURSOR0) &&\ (pipe_id <= MDSS_MDP_SSPP_CURSOR1)) #define IS_PIPE_TYPE_CURSOR(pipe_ndx) \ ((pipe_ndx >= (1 << MDSS_MDP_SSPP_CURSOR0)) &&\ (pipe_ndx <= (1 << MDSS_MDP_SSPP_CURSOR1))) enum { MDSS_MDP_RELEASE_FENCE = 0, Loading
drivers/video/msm/mdss/mdss_mdp_pipe.c +14 −3 Original line number Diff line number Diff line Loading @@ -1312,8 +1312,8 @@ static int mdss_mdp_is_pipe_idle(struct mdss_mdp_pipe *pipe, reg_val = readl_relaxed(mdata->mdp_base + pipe->clk_status.reg_off); if (reg_val & clk_status_idle_mask) is_idle = false; if ((reg_val & clk_status_idle_mask) == 0) is_idle = true; pr_debug("pipe#:%d clk_status:0x%x clk_status_idle_mask:0x%x\n", pipe->num, reg_val, clk_status_idle_mask); Loading @@ -1322,13 +1322,24 @@ static int mdss_mdp_is_pipe_idle(struct mdss_mdp_pipe *pipe, if (!ignore_force_on && (is_forced_on || !is_idle)) goto exit; /* * skip vbif check for cursor pipes as the same xin-id is shared * between cursor0, cursor1 and dsi */ if (pipe->type == MDSS_MDP_PIPE_TYPE_CURSOR) { if (ignore_force_on && is_forced_on) is_idle = true; goto exit; } vbif_idle_mask = BIT(pipe->xin_id + 16); reg_val = MDSS_VBIF_READ(mdata, MMSS_VBIF_XIN_HALT_CTRL1, is_nrt_vbif); if (reg_val & vbif_idle_mask) is_idle = true; pr_debug("pipe#:%d XIN_HALT_CTRL1: 0x%x\n", pipe->num, reg_val); pr_debug("pipe#:%d XIN_HALT_CTRL1: 0x%x, vbif_idle_mask: 0x%x\n", pipe->num, reg_val, vbif_idle_mask); exit: mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF); Loading