Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 535ff672 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge branch 'omap-clock-fixes' into omap-fixes

parents 846c29f1 f248076c

arch/arm/mach-omap1/mcbsp.c

+2 −2
Original line number Diff line number Diff line
@@ -40,8 +40,8 @@ static void omap1_mcbsp_request(unsigned int id) 
	 */

	if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {

		if (dsp_use++ == 0) {

			api_clk = clk_get(NULL, "api_clk");

			dsp_clk = clk_get(NULL, "dsp_clk");

			api_clk = clk_get(NULL, "api_ck");

			dsp_clk = clk_get(NULL, "dsp_ck");

			if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {

				clk_enable(api_clk);

				clk_enable(dsp_clk);

arch/arm/mach-omap2/board-omap3beagle.c

+4 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ 
#include <mach/nand.h>

#include <mach/mux.h>

#include <mach/usb.h>

#include <mach/timer-gp.h>



#include "mmc-twl4030.h"
@@ -186,6 +187,9 @@ static void __init omap3_beagle_init_irq(void) 
{

	omap2_init_common_hw(NULL);

	omap_init_irq();

#ifdef CONFIG_OMAP_32K_TIMER

	omap2_gp_clockevent_set_gptimer(12);

#endif

	omap_gpio_init();

}

arch/arm/mach-omap2/clock24xx.c

+7 −12
Original line number Diff line number Diff line
@@ -60,12 +60,13 @@ struct omap_clk { 
		},			\

	}



#define CK_243X	(1 << 0)

#define CK_242X	(1 << 1)

#define CK_243X			RATE_IN_243X

#define CK_242X			RATE_IN_242X



static struct omap_clk omap24xx_clks[] = {

	/* external root sources */

	CLK(NULL,	"func_32k_ck",	&func_32k_ck,	CK_243X | CK_242X),

	CLK(NULL,	"secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X),

	CLK(NULL,	"osc_ck",	&osc_ck,	CK_243X | CK_242X),

	CLK(NULL,	"sys_ck",	&sys_ck,	CK_243X | CK_242X),

	CLK(NULL,	"alt_ck",	&alt_ck,	CK_243X | CK_242X),
@@ -711,7 +712,7 @@ int __init omap2_clk_init(void) 
{

	struct prcm_config *prcm;

	struct omap_clk *c;

	u32 clkrate, cpu_mask;

	u32 clkrate;



	if (cpu_is_omap242x())

		cpu_mask = RATE_IN_242X;
@@ -720,20 +721,14 @@ int __init omap2_clk_init(void) 


	clk_init(&omap2_clk_functions);



	for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)

		clk_init_one(c->lk.clk);



	osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);

	propagate_rate(&osc_ck);

	sys_ck.rate = omap2_sys_clk_recalc(&sys_ck);

	propagate_rate(&sys_ck);



	for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)

		clk_init_one(c->lk.clk);



	cpu_mask = 0;

	if (cpu_is_omap2420())

		cpu_mask |= CK_242X;

	if (cpu_is_omap2430())

		cpu_mask |= CK_243X;



	for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)

		if (c->cpu & cpu_mask) {

			clkdev_add(&c->lk);

arch/arm/mach-omap2/clock24xx.h

+9 −1
Original line number Diff line number Diff line
@@ -625,6 +625,14 @@ static struct clk func_32k_ck = { 
	.clkdm_name	= "wkup_clkdm",

};



static struct clk secure_32k_ck = {

	.name		= "secure_32k_ck",

	.ops		= &clkops_null,

	.rate		= 32768,

	.flags		= RATE_FIXED,

	.clkdm_name	= "wkup_clkdm",

};



/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */

static struct clk osc_ck = {		/* (*12, *13, 19.2, *26, 38.4)MHz */

	.name		= "osc_ck",
@@ -1790,7 +1798,7 @@ static struct clk gpt12_ick = { 
static struct clk gpt12_fck = {

	.name		= "gpt12_fck",

	.ops		= &clkops_omap2_dflt_wait,

	.parent		= &func_32k_ck,

	.parent		= &secure_32k_ck,

	.clkdm_name	= "core_l4_clkdm",

	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),

	.enable_bit	= OMAP24XX_EN_GPT12_SHIFT,

arch/arm/mach-omap2/clock34xx.h

+3 −4
Original line number Diff line number Diff line
@@ -2052,7 +2052,7 @@ static struct clk dss_ick = { 


static struct clk cam_mclk = {

	.name		= "cam_mclk",

	.ops		= &clkops_omap2_dflt_wait,

	.ops		= &clkops_omap2_dflt,

	.parent		= &dpll4_m5x2_ck,

	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),

	.enable_bit	= OMAP3430_EN_CAM_SHIFT,
@@ -2063,7 +2063,7 @@ static struct clk cam_mclk = { 
static struct clk cam_ick = {

	/* Handles both L3 and L4 clocks */

	.name		= "cam_ick",

	.ops		= &clkops_omap2_dflt_wait,

	.ops		= &clkops_omap2_dflt,

	.parent		= &l4_ick,

	.init		= &omap2_init_clk_clkdm,

	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
@@ -2074,7 +2074,7 @@ static struct clk cam_ick = { 


static struct clk csi2_96m_fck = {

	.name		= "csi2_96m_fck",

	.ops		= &clkops_omap2_dflt_wait,

	.ops		= &clkops_omap2_dflt,

	.parent		= &core_96m_fck,

	.init		= &omap2_init_clk_clkdm,

	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
@@ -2901,7 +2901,6 @@ static struct clk sr_l4_ick = { 


/* SECURE_32K_FCK clocks */



/* XXX This clock no longer exists in 3430 TRM rev F */

static struct clk gpt12_fck = {

	.name		= "gpt12_fck",

	.ops		= &clkops_null,