Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 534843da authored by Chris Wilson's avatar Chris Wilson Committed by Eric Anholt
Browse files

drm/i915: Use 128k alignment for untiled display surface on i965 (v2) 



The original i965, including the revised G35 and Q35, requires an
alignment of 128K for the display surface with linear memory, so
increase the requirement from 64k for these chipsets. For the later
chipsets in the i965 family, only a 4k alignment is required. (So
long as we do not start performing asynchronous flips.)

Note the impact of this should be slight as on i965 we should be using a
tiled frontbuffer for anything up to a 4096x4096 display.

v2: compilation fixes and note that the docs do not exclude the G35 from
the extra alignment.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent e1a44743

drivers/gpu/drm/i915/i915_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -93,11 +93,11 @@ static const struct intel_device_info intel_i945gm_info = { 
};



static const struct intel_device_info intel_i965g_info = {

	.is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,

	.is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,

};



static const struct intel_device_info intel_i965gm_info = {

	.is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,

	.is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,

	.is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,

	.has_hotplug = 1,

};

drivers/gpu/drm/i915/i915_drv.h

+4 −0
Original line number Diff line number Diff line
@@ -201,6 +201,8 @@ struct intel_device_info { 
	u8 need_gfx_hws : 1;

	u8 is_g4x : 1;

	u8 is_pineview : 1;

	u8 is_broadwater : 1;

	u8 is_crestline : 1;

	u8 is_ironlake : 1;

	u8 is_gen6 : 1;

	u8 has_fbc : 1;
@@ -1134,6 +1136,8 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); 
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)

#define IS_I965G(dev)		(INTEL_INFO(dev)->is_i965g)

#define IS_I965GM(dev)		(INTEL_INFO(dev)->is_i965gm)

#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)

#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)

#define IS_GM45(dev)		((dev)->pci_device == 0x2A42)

#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)

#define IS_PINEVIEW_G(dev)	((dev)->pci_device == 0xa001)

drivers/gpu/drm/i915/intel_display.c

+6 −1
Original line number Diff line number Diff line
@@ -1329,6 +1329,11 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj) 


	switch (obj_priv->tiling_mode) {

	case I915_TILING_NONE:

		if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))

			alignment = 128 * 1024;

		else if (IS_I965G(dev))

			alignment = 4 * 1024;

		else

			alignment = 64 * 1024;

		break;

	case I915_TILING_X: