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Commit 5341fe96 authored by Carter Cooper's avatar Carter Cooper Committed by Jordan Crouse
Browse files

msm: kgsl: Add feature to enable 64 bit GPU addresses 



Add a device feature flag to allow the GPU to use 64 bit
addresses.

Change-Id: I03d9ff7dffded776c9ae3629e10cc6a3db8492c7
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
Signed-off-by: default avatarShrenuj Bansal <shrenujb@codeaurora.org>
parent f8435720

drivers/gpu/msm/a5xx_reg.h

+14 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ 
#define A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI   0x83F

#define A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO   0x840

#define A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI   0x841

#define A5XX_CP_ADDR_MODE_CNTL           0x860

#define A5XX_CP_ME_STAT_DATA             0xB14

#define A5XX_CP_WFI_PEND_CTR             0xB15

#define A5XX_CP_INTERRUPT_STATUS         0xB18
@@ -118,6 +119,8 @@ 
#define A5XX_CP_PERFCTR_CP_SEL_6         0xBB6

#define A5XX_CP_PERFCTR_CP_SEL_7         0xBB7



#define A5XX_VSC_ADDR_MODE_CNTL          0xBC1



/* CP Power Counter Registers Select */

#define A5XX_CP_POWERCTR_CP_SEL_0        0xBBA

#define A5XX_CP_POWERCTR_CP_SEL_1        0xBBB
@@ -535,6 +538,8 @@ 
#define A5XX_VSC_PERFCTR_VSC_SEL_0          0xC60

#define A5XX_VSC_PERFCTR_VSC_SEL_1          0xC61



#define A5XX_GRAS_ADDR_MODE_CNTL            0xC81



/* TSE registers */

#define A5XX_GRAS_PERFCTR_TSE_SEL_0         0xC90

#define A5XX_GRAS_PERFCTR_TSE_SEL_1         0xC91
@@ -555,6 +560,7 @@ 




/* RB registers */

#define A5XX_RB_ADDR_MODE_CNTL              0xCC5

#define A5XX_RB_PERFCTR_RB_SEL_0            0xCD0

#define A5XX_RB_PERFCTR_RB_SEL_1            0xCD1

#define A5XX_RB_PERFCTR_RB_SEL_2            0xCD2
@@ -588,6 +594,7 @@ 


/* PC registers */

#define A5XX_PC_DBG_ECO_CNTL                0xD00

#define A5XX_PC_ADDR_MODE_CNTL              0xD01

#define A5XX_PC_PERFCTR_PC_SEL_0            0xD10

#define A5XX_PC_PERFCTR_PC_SEL_1            0xD11

#define A5XX_PC_PERFCTR_PC_SEL_2            0xD12
@@ -599,6 +606,7 @@ 


/* HLSQ registers */

#define A5XX_HLSQ_TIMEOUT_THRESHOLD         0xE00

#define A5XX_HLSQ_ADDR_MODE_CNTL            0xE05

#define A5XX_HLSQ_PERFCTR_HLSQ_SEL_0        0xE10

#define A5XX_HLSQ_PERFCTR_HLSQ_SEL_1        0xE11

#define A5XX_HLSQ_PERFCTR_HLSQ_SEL_2        0xE12
@@ -612,6 +620,7 @@ 
#define A5XX_HLSQ_DBG_AHB_READ_APERTURE     0xA000



/* VFD registers */

#define A5XX_VFD_ADDR_MODE_CNTL             0xE41

#define A5XX_VFD_PERFCTR_VFD_SEL_0          0xE50

#define A5XX_VFD_PERFCTR_VFD_SEL_1          0xE51

#define A5XX_VFD_PERFCTR_VFD_SEL_2          0xE52
@@ -622,12 +631,15 @@ 
#define A5XX_VFD_PERFCTR_VFD_SEL_7          0xE57



/* VPC registers */

#define A5XX_VPC_ADDR_MODE_CNTL             0xE61

#define A5XX_VPC_PERFCTR_VPC_SEL_0          0xE64

#define A5XX_VPC_PERFCTR_VPC_SEL_1          0xE65

#define A5XX_VPC_PERFCTR_VPC_SEL_2          0xE66

#define A5XX_VPC_PERFCTR_VPC_SEL_3          0xE67



/* UCHE registers */

#define A5XX_UCHE_ADDR_MODE_CNTL            0xE80

#define A5XX_UCHE_SVM_CNTL                  0xE82

#define A5XX_UCHE_WRITE_THRU_BASE_LO        0xE87

#define A5XX_UCHE_WRITE_THRU_BASE_HI        0xE88

#define A5XX_UCHE_TRAP_BASE_LO              0xE89
@@ -655,6 +667,7 @@ 


/* SP registers */

#define A5XX_SP_DBG_ECO_CNTL                0xEC0

#define A5XX_SP_ADDR_MODE_CNTL              0xEC1

#define A5XX_SP_PERFCTR_SP_SEL_0            0xED0

#define A5XX_SP_PERFCTR_SP_SEL_1            0xED1

#define A5XX_SP_PERFCTR_SP_SEL_2            0xED2
@@ -675,6 +688,7 @@ 
#define A5XX_SP_POWERCTR_SP_SEL_3           0xEDF



/* TP registers */

#define A5XX_TPL1_ADDR_MODE_CNTL            0xF01

#define A5XX_TPL1_PERFCTR_TP_SEL_0          0xF10

#define A5XX_TPL1_PERFCTR_TP_SEL_1          0xF11

#define A5XX_TPL1_PERFCTR_TP_SEL_2          0xF12

drivers/gpu/msm/adreno.c

+5 −0
Original line number Diff line number Diff line
@@ -1403,6 +1403,11 @@ static int _adreno_start(struct adreno_device *adreno_dev) 
		goto error_mmu_off;

	}



	/* Enable 64 bit gpu addr if feature is set */

	if (gpudev->enable_64bit &&

			ADRENO_FEATURE(adreno_dev, ADRENO_64BIT))

		gpudev->enable_64bit(adreno_dev);



	if (adreno_dev->perfctr_pwr_lo == 0) {

		int ret = adreno_perfcounter_get(adreno_dev,

			KGSL_PERFCOUNTER_GROUP_PWR, 1,

drivers/gpu/msm/adreno.h

+3 −0
Original line number Diff line number Diff line
@@ -102,6 +102,8 @@ 
#define ADRENO_GPMU BIT(8)

/* The GPMU supports Limits Management */

#define ADRENO_LM BIT(9)

/* The core uses 64 bit GPU addresses */

#define ADRENO_64BIT BIT(10)



/* Flags to control command packet settings */

#define KGSL_CMD_FLAGS_NONE             0
@@ -670,6 +672,7 @@ struct adreno_gpudev { 
				uint64_t gpuaddr);

	void (*preemption_init)(struct adreno_device *);

	void (*preemption_schedule)(struct adreno_device *);

	void (*enable_64bit)(struct adreno_device *);

};



struct log_field {

drivers/gpu/msm/adreno_a5xx.c

+19 −0
Original line number Diff line number Diff line
@@ -1330,6 +1330,24 @@ static void a5xx_pwrlevel_change_settings(struct adreno_device *adreno_dev, 
	}

}



static void a5xx_enable_64bit(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = &adreno_dev->dev;



	kgsl_regwrite(device, A5XX_CP_ADDR_MODE_CNTL, 0x1);

	kgsl_regwrite(device, A5XX_VSC_ADDR_MODE_CNTL, 0x1);

	kgsl_regwrite(device, A5XX_GRAS_ADDR_MODE_CNTL, 0x1);

	kgsl_regwrite(device, A5XX_RB_ADDR_MODE_CNTL, 0x1);

	kgsl_regwrite(device, A5XX_PC_ADDR_MODE_CNTL, 0x1);

	kgsl_regwrite(device, A5XX_HLSQ_ADDR_MODE_CNTL, 0x1);

	kgsl_regwrite(device, A5XX_VFD_ADDR_MODE_CNTL, 0x1);

	kgsl_regwrite(device, A5XX_VPC_ADDR_MODE_CNTL, 0x1);

	kgsl_regwrite(device, A5XX_UCHE_ADDR_MODE_CNTL, 0x1);

	kgsl_regwrite(device, A5XX_SP_ADDR_MODE_CNTL, 0x1);

	kgsl_regwrite(device, A5XX_TPL1_ADDR_MODE_CNTL, 0x1);

	kgsl_regwrite(device, A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);

}



/*

 * a5xx_start() - Device start

 * @adreno_dev: Pointer to adreno device
@@ -2980,4 +2998,5 @@ struct adreno_gpudev adreno_a5xx_gpudev = { 
	.preemption_init = a5xx_preemption_init,

	.gpmu_start = a5xx_gpmu_start,

	.preemption_schedule = a5xx_preemption_schedule,

	.enable_64bit = a5xx_enable_64bit,

};