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Commit 5323264c authored by Subbaraman Narayanamurthy's avatar Subbaraman Narayanamurthy
Browse files

power: qpnp-fg: Return error properly when IMA read/write fails 



In the SRAM masked write we read the register first, make
modification to the value and write it back. If the read fails
we bail out of the masked write function.

However there is a bug in the read api where the error code is
not properly returned. This causes the masked write to proceed
with a failed read and corruption ensues.

A similar bug is present in write api too where the error is not
returned correctly to the caller. Fix this. While at it, take the
opportunity to improve debug logs.

Change-Id: Ic7651c5cb2e054a0b8b2dfe201463063ce9e167b
Signed-off-by: default avatarSubbaraman Narayanamurthy <subbaram@codeaurora.org>
parent 7ec5d79a

drivers/power/qpnp-fg.c

+21 −12
Original line number Diff line number Diff line
@@ -1544,7 +1544,8 @@ static int __fg_interleaved_mem_write(struct fg_chip *chip, u8 *val, 


		rc = fg_check_iacs_ready(chip);

		if (rc) {

			pr_debug("IACS_RDY failed rc=%d\n", rc);

			pr_err("IACS_RDY failed post write to address %x offset %d rc=%d\n",

				address, offset, rc);

			return rc;

		}
@@ -1590,7 +1591,8 @@ static int __fg_interleaved_mem_read(struct fg_chip *chip, u8 *val, u16 address, 


		rc = fg_check_iacs_ready(chip);

		if (rc) {

			pr_debug("IACS_RDY failed rc=%d\n", rc);

			pr_err("IACS_RDY failed post read for address %x offset %d rc=%d\n",

				address, offset, rc);

			return rc;

		}
@@ -1673,7 +1675,8 @@ static int fg_interleaved_mem_config(struct fg_chip *chip, u8 *val, 


	rc = fg_check_iacs_ready(chip);

	if (rc) {

		pr_debug("IACS_RDY failed rc=%d\n", rc);

		pr_err("IACS_RDY failed before setting address: %x offset: %d rc=%d\n",

			address, offset, rc);

		return rc;

	}
@@ -1686,7 +1689,8 @@ static int fg_interleaved_mem_config(struct fg_chip *chip, u8 *val, 


	rc = fg_check_iacs_ready(chip);

	if (rc)

		pr_debug("IACS_RDY failed rc=%d\n", rc);

		pr_err("IACS_RDY failed after setting address: %x offset: %d rc=%d\n",

			address, offset, rc);



	return rc;

}
@@ -1697,7 +1701,7 @@ static int fg_interleaved_mem_config(struct fg_chip *chip, u8 *val, 
static int fg_interleaved_mem_read(struct fg_chip *chip, u8 *val, u16 address,

						int len, int offset)

{

	int rc = 0, orig_address = address;

	int rc = 0, ret, orig_address = address;

	u8 start_beat_count, end_beat_count, count = 0;

	bool retry = false;
@@ -1778,9 +1782,14 @@ retry: 
	}

out:

	/* Release IMA access */

	rc = fg_masked_write(chip, MEM_INTF_CFG(chip), IMA_REQ_ACCESS, 0, 1);

	if (rc)

		pr_err("failed to reset IMA access bit rc = %d\n", rc);

	ret = fg_masked_write(chip, MEM_INTF_CFG(chip), IMA_REQ_ACCESS, 0, 1);

	if (ret)

		pr_err("failed to reset IMA access bit ret = %d\n", ret);



	if (rc) {

		mutex_unlock(&chip->rw_lock);

		goto exit;

	}



	if (retry) {

		retry = false;
@@ -1796,7 +1805,7 @@ exit: 
static int fg_interleaved_mem_write(struct fg_chip *chip, u8 *val, u16 address,

							int len, int offset)

{

	int rc = 0, orig_address = address;

	int rc = 0, ret, orig_address = address;

	u8 count = 0;



	if (chip->fg_shutdown)
@@ -1841,9 +1850,9 @@ retry: 


out:

	/* Release IMA access */

	rc = fg_masked_write(chip, MEM_INTF_CFG(chip), IMA_REQ_ACCESS, 0, 1);

	if (rc)

		pr_err("failed to reset IMA access bit rc = %d\n", rc);

	ret = fg_masked_write(chip, MEM_INTF_CFG(chip), IMA_REQ_ACCESS, 0, 1);

	if (ret)

		pr_err("failed to reset IMA access bit ret = %d\n", ret);



	mutex_unlock(&chip->rw_lock);

	fg_relax(&chip->memif_wakeup_source);