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Commit 5309227b authored by Amit Atreya's avatar Amit Atreya Committed by Prasad Sodagudi
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ARM: dts: msm: Add ERP dts entry for msmtitanium 



Add ERP DTS entries for msmtitanium to support L1/L2
cache memory error detection and correction support.

Change-Id: I4efb79f0c3410be3ee3f1837dd78255c5711d844
Signed-off-by: default avatarAmit Atreya <aatrey@codeaurora.org>
parent 19240e8d
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