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Commit 5309227b authored by Amit Atreya's avatar Amit Atreya Committed by Prasad Sodagudi
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ARM: dts: msm: Add ERP dts entry for msmtitanium 



Add ERP DTS entries for msmtitanium to support L1/L2
cache memory error detection and correction support.

Change-Id: I4efb79f0c3410be3ee3f1837dd78255c5711d844
Signed-off-by: default avatarAmit Atreya <aatrey@codeaurora.org>
parent 19240e8d

arch/arm/boot/dts/qcom/msmtitanium.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -137,6 +137,19 @@ 
		      <0x0b002000 0x1000>;

	};



	arm64-cpu-erp {

		compatible = "arm,arm64-cpu-erp";

		interrupts = <0 275 0>,

			     <0 276 0>,

			     <0 273 0>,

			     <0 274 0>;

		interrupt-names = "pri-dbe-irq",

				  "sec-dbe-irq",

				  "pri-ext-irq",

				  "sec-ext-irq";

		poll-delay-ms = <5000>;

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <1 2 0xff08>,