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Commit 524cd267 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge branch 'for-3.6/common-clk' of... 

Merge branch 'for-3.6/common-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/clk

From Stephen Warren <swarren@wwwdotorg.org>:

This branch contains numerous changes required as a baseline in order to
convert Tegra to the common clock framework. The intention was to also
include patches to actually convert Tegra to the common clock framework.
However, those patches appeared late in the kernel cycle and currently
cause regressions on some boards, so were dropped for now.

* 'for-3.6/common-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra

:
  ARM: tegra: Provide clock for only one PWM controller
  ARM: tegra: Fix PWM clock programming
  ARM: tegra: dma: rename driver name for clock to "tegra-apbdma"
  ARM: tegra: Remove second instance of uart clk
  crypto: add clk_prepare/clk_unprepare
  ASoC: tegra: add clk_prepare/clk_unprepare
  staging: nvec: add clk_prepare/clk_unprepare
  spi/tegra: add clk_prepare/clk_unprepare
  Input: tegra-kbc - add clk_prepare/clk_unprepare
  USB: ehci-tegra: add clk_prepare/clk_unprepare
  mmc: tegra: add clk_prepare/clk_unprepare
  i2c: tegra: Add clk_prepare/clk_unprepare
  ARM: tegra: add clk_prepare/clk_unprepare

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents ebaaa25d 09447991

arch/arm/mach-tegra/cpu-tegra.c

+3 −3
Original line number Diff line number Diff line
@@ -189,8 +189,8 @@ static int tegra_cpu_init(struct cpufreq_policy *policy) 
		return PTR_ERR(emc_clk);

	}



	clk_enable(emc_clk);

	clk_enable(cpu_clk);

	clk_prepare_enable(emc_clk);

	clk_prepare_enable(cpu_clk);



	cpufreq_frequency_table_cpuinfo(policy, freq_table);

	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
@@ -212,7 +212,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy) 
static int tegra_cpu_exit(struct cpufreq_policy *policy)

{

	cpufreq_frequency_table_cpuinfo(policy, freq_table);

	clk_disable(emc_clk);

	clk_disable_unprepare(emc_clk);

	clk_put(emc_clk);

	clk_put(cpu_clk);

	return 0;

arch/arm/mach-tegra/dma.c

+2 −2
Original line number Diff line number Diff line
@@ -714,13 +714,13 @@ int __init tegra_dma_init(void) 


	bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS);



	c = clk_get_sys("tegra-dma", NULL);

	c = clk_get_sys("tegra-apbdma", NULL);

	if (IS_ERR(c)) {

		pr_err("Unable to get clock for APB DMA\n");

		ret = PTR_ERR(c);

		goto fail;

	}

	ret = clk_enable(c);

	ret = clk_prepare_enable(c);

	if (ret != 0) {

		pr_err("Unable to enable clock for APB DMA\n");

		goto fail;

arch/arm/mach-tegra/pcie.c

+3 −3
Original line number Diff line number Diff line
@@ -723,9 +723,9 @@ static int tegra_pcie_power_regate(void) 


	tegra_pcie_xclk_clamp(false);



	clk_enable(tegra_pcie.afi_clk);

	clk_enable(tegra_pcie.pex_clk);

	return clk_enable(tegra_pcie.pll_e);

	clk_prepare_enable(tegra_pcie.afi_clk);

	clk_prepare_enable(tegra_pcie.pex_clk);

	return clk_prepare_enable(tegra_pcie.pll_e);

}



static int tegra_pcie_clocks_get(void)

arch/arm/mach-tegra/powergate.c

+2 −2
Original line number Diff line number Diff line
@@ -146,7 +146,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk) 
	if (ret)

		goto err_power;



	ret = clk_enable(clk);

	ret = clk_prepare_enable(clk);

	if (ret)

		goto err_clk;
@@ -162,7 +162,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk) 
	return 0;



err_clamp:

	clk_disable(clk);

	clk_disable_unprepare(clk);

err_clk:

	tegra_powergate_power_off(id);

err_power:

arch/arm/mach-tegra/tegra2_clocks.c

+39 −19
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ 


#define PERIPH_CLK_SOURCE_MASK		(3<<30)

#define PERIPH_CLK_SOURCE_SHIFT		30

#define PERIPH_CLK_SOURCE_PWM_MASK	(7<<28)

#define PERIPH_CLK_SOURCE_PWM_SHIFT	28

#define PERIPH_CLK_SOURCE_ENABLE	(1<<28)

#define PERIPH_CLK_SOURCE_DIVU71_MASK	0xFF

#define PERIPH_CLK_SOURCE_DIVU16_MASK	0xFFFF
@@ -908,9 +910,20 @@ static void tegra2_periph_clk_init(struct clk *c) 
	u32 val = clk_readl(c->reg);

	const struct clk_mux_sel *mux = NULL;

	const struct clk_mux_sel *sel;

	u32 shift;

	u32 mask;



	if (c->flags & MUX_PWM) {

		shift = PERIPH_CLK_SOURCE_PWM_SHIFT;

		mask = PERIPH_CLK_SOURCE_PWM_MASK;

	} else {

		shift = PERIPH_CLK_SOURCE_SHIFT;

		mask = PERIPH_CLK_SOURCE_MASK;

	}



	if (c->flags & MUX) {

		for (sel = c->inputs; sel->input != NULL; sel++) {

			if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)

			if ((val & mask) >> shift == sel->value)

				mux = sel;

		}

		BUG_ON(!mux);
@@ -1023,12 +1036,23 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p) 
{

	u32 val;

	const struct clk_mux_sel *sel;

	u32 mask, shift;



	pr_debug("%s: %s %s\n", __func__, c->name, p->name);



	if (c->flags & MUX_PWM) {

		shift = PERIPH_CLK_SOURCE_PWM_SHIFT;

		mask = PERIPH_CLK_SOURCE_PWM_MASK;

	} else {

		shift = PERIPH_CLK_SOURCE_SHIFT;

		mask = PERIPH_CLK_SOURCE_MASK;

	}



	for (sel = c->inputs; sel->input != NULL; sel++) {

		if (sel->input == p) {

			val = clk_readl(c->reg);

			val &= ~PERIPH_CLK_SOURCE_MASK;

			val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;

			val &= ~mask;

			val |= (sel->value) << shift;



			if (c->refcnt)

				clk_enable(p);
@@ -2149,14 +2173,14 @@ static struct clk tegra_clk_emc = { 
	}



static struct clk tegra_list_clks[] = {

	PERIPH_CLK("apbdma",	"tegra-dma",		NULL,	34,	0,	108000000, mux_pclk,			0),

	PERIPH_CLK("apbdma",	"tegra-apbdma",		NULL,	34,	0,	108000000, mux_pclk,			0),

	PERIPH_CLK("rtc",	"rtc-tegra",		NULL,	4,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET),

	PERIPH_CLK("timer",	"timer",		NULL,	5,	0,	26000000,  mux_clk_m,			0),

	PERIPH_CLK("i2s1",	"tegra20-i2s.0",	NULL,	11,	0x100,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),

	PERIPH_CLK("i2s2",	"tegra20-i2s.1",	NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),

	PERIPH_CLK("spdif_out",	"spdif_out",		NULL,	10,	0x108,	100000000, mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),

	PERIPH_CLK("spdif_in",	"spdif_in",		NULL,	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71),

	PERIPH_CLK("pwm",	"pwm",			NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71),

	PERIPH_CLK("pwm",	"tegra-pwm",		NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71 | MUX_PWM),

	PERIPH_CLK("spi",	"spi",			NULL,	43,	0x114,	40000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),

	PERIPH_CLK("xio",	"xio",			NULL,	45,	0x120,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),

	PERIPH_CLK("twc",	"twc",			NULL,	16,	0x12c,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
@@ -2189,11 +2213,11 @@ static struct clk tegra_list_clks[] = { 
	PERIPH_CLK("i2c2_i2c",	"tegra-i2c.1",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),

	PERIPH_CLK("i2c3_i2c",	"tegra-i2c.2",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),

	PERIPH_CLK("dvc_i2c",	"tegra-i2c.3",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),

	PERIPH_CLK("uarta",	"uart.0",		NULL,	6,	0x178,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),

	PERIPH_CLK("uartb",	"uart.1",		NULL,	7,	0x17c,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),

	PERIPH_CLK("uartc",	"uart.2",		NULL,	55,	0x1a0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),

	PERIPH_CLK("uartd",	"uart.3",		NULL,	65,	0x1c0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),

	PERIPH_CLK("uarte",	"uart.4",		NULL,	66,	0x1c4,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),

	PERIPH_CLK("uarta",	"tegra-uart.0",		NULL,	6,	0x178,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),

	PERIPH_CLK("uartb",	"tegra-uart.1",		NULL,	7,	0x17c,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),

	PERIPH_CLK("uartc",	"tegra-uart.2",		NULL,	55,	0x1a0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),

	PERIPH_CLK("uartd",	"tegra-uart.3",		NULL,	65,	0x1c0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),

	PERIPH_CLK("uarte",	"tegra-uart.4",		NULL,	66,	0x1c4,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),

	PERIPH_CLK("3d",	"3d",			NULL,	24,	0x158,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */

	PERIPH_CLK("2d",	"2d",			NULL,	21,	0x15c,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */

	PERIPH_CLK("vi",	"tegra_camera",		"vi",	20,	0x148,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
@@ -2245,20 +2269,16 @@ static struct clk tegra_list_clks[] = { 
 * table under two names.

 */

static struct clk_duplicate tegra_clk_duplicates[] = {

	CLK_DUPLICATE("uarta",	"tegra_uart.0",	NULL),

	CLK_DUPLICATE("uartb",	"tegra_uart.1",	NULL),

	CLK_DUPLICATE("uartc",	"tegra_uart.2",	NULL),

	CLK_DUPLICATE("uartd",	"tegra_uart.3",	NULL),

	CLK_DUPLICATE("uarte",	"tegra_uart.4",	NULL),

	CLK_DUPLICATE("uarta",  "serial8250.0", NULL),

	CLK_DUPLICATE("uartb",  "serial8250.1", NULL),

	CLK_DUPLICATE("uartc",  "serial8250.2", NULL),

	CLK_DUPLICATE("uartd",  "serial8250.3", NULL),

	CLK_DUPLICATE("uarte",  "serial8250.4", NULL),

	CLK_DUPLICATE("usbd", "utmip-pad", NULL),

	CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),

	CLK_DUPLICATE("usbd", "tegra-otg", NULL),

	CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),

	CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),

	CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),

	CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),

	CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),

	CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),

	CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),

	CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),

	CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),