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Commit 51198baa authored by Jordan Crouse's avatar Jordan Crouse Committed by Jeremy Gebben
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msm: kgsl: Make an interface to write A5XX clock gating registers 



We will have more 5XX targets with ever increasing hardware clock
gating requirements. Rather than piling on if/else statements create
a generic infrastructure to write the correct sets of registers.

Change-Id: Ic0dedbad0a18df87a68858045b2662b3470b1276
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent e6e315ee

drivers/gpu/msm/adreno.h

+6 −0
Original line number Diff line number Diff line
@@ -951,6 +951,12 @@ static inline int adreno_is_a530v1(struct adreno_device *adreno_dev) 
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 0);

}



static inline int adreno_is_a530v2(struct adreno_device *adreno_dev)

{

	return (ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A530) &&

		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) != 0);

}



static inline int adreno_is_a510(struct adreno_device *adreno_dev)

{

	return ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A510;

drivers/gpu/msm/adreno_a5xx.c

+28 −12
Original line number Diff line number Diff line
@@ -944,13 +944,34 @@ static const struct kgsl_hwcg_reg a530_hwcg_regs[] = { 
	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}

};



static void a5xx_hwcg_init(struct kgsl_device *device,

	const struct kgsl_hwcg_reg *regs, unsigned int nregs)

static const struct {

	int (*devfunc)(struct adreno_device *adreno_dev);

	const struct kgsl_hwcg_reg *regs;

	unsigned int count;

} a5xx_hwcg_registers[] = {

	{ adreno_is_a530v2, a530_hwcg_regs, ARRAY_SIZE(a530_hwcg_regs) },

	{ adreno_is_a510, a510_hwcg_regs, ARRAY_SIZE(a510_hwcg_regs) },

};



static void a5xx_hwcg_init(struct adreno_device *adreno_dev)

{

	unsigned int i;

	/* program revision specific HWCG settings */

	for (i = 0; i < nregs; i++)

		kgsl_regwrite(device, regs[i].off, regs[i].val);

	struct kgsl_device *device = &adreno_dev->dev;

	const struct kgsl_hwcg_reg *regs;

	int i, j;



	for (i = 0; i < ARRAY_SIZE(a5xx_hwcg_registers); i++) {

		if (a5xx_hwcg_registers[i].devfunc(adreno_dev))

			break;

	}



	if (i == ARRAY_SIZE(a5xx_hwcg_registers))

		return;



	regs = a5xx_hwcg_registers[i].regs;



	for (j = 0; j < a5xx_hwcg_registers[i].count; j++)

		kgsl_regwrite(device, regs[j].off, regs[j].val);



	/* enable top level HWCG */

	kgsl_regwrite(device, A5XX_RBBM_CLOCK_CNTL, 0xAAA8AA00);

	kgsl_regwrite(device, A5XX_RBBM_ISDB_CNT, 0x00000182);
@@ -1420,12 +1441,7 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
	/* Set the USE_RETENTION_FLOPS chicken bit */

	kgsl_regwrite(device, A5XX_CP_CHICKEN_DBG, 0x02000000);



	if (adreno_is_a530(adreno_dev) && !adreno_is_a530v1(adreno_dev))

		a5xx_hwcg_init(device, a530_hwcg_regs,

			ARRAY_SIZE(a530_hwcg_regs));

	else if (adreno_is_a510(adreno_dev))

		a5xx_hwcg_init(device, a510_hwcg_regs,

			ARRAY_SIZE(a510_hwcg_regs));

	a5xx_hwcg_init(adreno_dev);



	a5xx_protect_init(adreno_dev);

}