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Commit 50118e60 authored by Deepak Katragadda's avatar Deepak Katragadda Committed by Matt Wagantall
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soc: qcom: pil: Proxy vote for the QDSS clocks during modem boot 



During modem boot, PBL might need to access the STM hardware
registers and thus needs the QDSS clock to be enabled at that
time. Put in a proxy vote from HLOS PIL which is removed once
the modem boots up.

Change-Id: I3d47a54b96a6ebe781a8786901423f304876a170
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 7470f022

arch/arm/boot/dts/qcom/msm8996.dtsi

+4 −3
Original line number Diff line number Diff line
@@ -2392,11 +2392,12 @@ 
			 <&clock_gcc clk_gcc_boot_rom_ahb_clk>,

			 <&clock_gcc clk_gpll0_out_msscc>,

			 <&clock_gcc clk_gcc_mss_snoc_axi_clk>,

			 <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>;

			 <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>,

			 <&clock_gcc clk_qdss_clk>;

		clock-names = "xo", "iface_clk", "pnoc_clk", "bus_clk",

			      "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",

			      "mnoc_axi_clk";

		qcom,proxy-clock-names = "xo", "pnoc_clk";

			      "mnoc_axi_clk", "qdss_clk";

		qcom,proxy-clock-names = "xo", "pnoc_clk", "qdss_clk";

		qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",

					  "gpll0_mss_clk", "snoc_axi_clk",

					  "mnoc_axi_clk";

drivers/soc/qcom/pil-q6v5.c

+18 −0
Original line number Diff line number Diff line
@@ -95,6 +95,12 @@ int pil_q6v5_make_proxy_votes(struct pil_desc *pil) 
		goto err_pnoc_vote;

	}



	ret = clk_prepare_enable(drv->qdss_clk);

	if (ret) {

		dev_err(pil->dev, "Failed to vote for qdss\n");

		goto err_qdss_vote;

	}



	ret = regulator_set_voltage(drv->vreg_cx,

				    RPM_REGULATOR_CORNER_SUPER_TURBO,

				    RPM_REGULATOR_CORNER_SUPER_TURBO);
@@ -133,6 +139,8 @@ err_cx_mode: 
	regulator_set_voltage(drv->vreg_cx, RPM_REGULATOR_CORNER_NONE,

			      RPM_REGULATOR_CORNER_SUPER_TURBO);

err_cx_voltage:

	clk_disable_unprepare(drv->qdss_clk);

err_qdss_vote:

	clk_disable_unprepare(drv->pnoc_clk);

err_pnoc_vote:

	clk_disable_unprepare(drv->xo);
@@ -155,6 +163,7 @@ void pil_q6v5_remove_proxy_votes(struct pil_desc *pil) 
			      RPM_REGULATOR_CORNER_SUPER_TURBO);

	clk_disable_unprepare(drv->xo);

	clk_disable_unprepare(drv->pnoc_clk);

	clk_disable_unprepare(drv->qdss_clk);

}

EXPORT_SYMBOL(pil_q6v5_remove_proxy_votes);
@@ -533,6 +542,15 @@ struct q6v5_data *pil_q6v5_init(struct platform_device *pdev) 
		drv->pnoc_clk = NULL;

	}



	if (of_property_match_string(pdev->dev.of_node,

			"qcom,proxy-clock-names", "qdss_clk") >= 0) {

		drv->qdss_clk = devm_clk_get(&pdev->dev, "qdss_clk");

		if (IS_ERR(drv->qdss_clk))

			return ERR_CAST(drv->qdss_clk);

	} else {

		drv->qdss_clk = NULL;

	}



	drv->vreg_cx = devm_regulator_get(&pdev->dev, "vdd_cx");

	if (IS_ERR(drv->vreg_cx))

		return ERR_CAST(drv->vreg_cx);

drivers/soc/qcom/pil-q6v5.h

+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ struct q6v5_data { 
	struct clk *rom_clk;	   /* Boot ROM */

	struct clk *snoc_axi_clk;

	struct clk *mnoc_axi_clk;

	struct clk *qdss_clk;

	void __iomem *axi_halt_base; /* Halt base of q6, mss,

					nc are in same 4K page */

	void __iomem *axi_halt_q6;