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Commit 4fe343f9 authored by Vince Leung's avatar Vince Leung Committed by Sanrio Alvares
Browse files

arm64: entry: add support for CONFIG_ARM64_REG_REBALANCE_ON_CTX_SW 



Add support for re-balancing register rename pools on context
switches, for a potential performance boost on some ARM64 targets.

Change-Id: I7577c11fac566ae91a210787c70b23591bfbd693
Signed-off-by: default avatarSanrio Alvares <salvares@codeaurora.org>
parent f1d461b6

arch/arm64/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -630,6 +630,13 @@ config PERF_EVENTS_RESET_PMU_DEBUGFS 
		If you want to reset PMU and PMU related internal Perf variables

		via debugfs then say Y.



config ARM64_REG_REBALANCE_ON_CTX_SW

	bool "Rebalance registers during context switches."

	def_bool ARCH_MSM8996

	help

	 Forcefully re-balance register rename pools on context switches for

	 improved performance on some devices.



config SYS_SUPPORTS_HUGETLBFS

	def_bool y

arch/arm64/kernel/entry.S

+27 −0
Original line number Diff line number Diff line
@@ -600,6 +600,33 @@ ENTRY(cpu_switch_to) 
	ldp	x27, x28, [x8], #16

	ldp	x29, x9, [x8], #16

	ldr	lr, [x8]

#ifdef CONFIG_ARM64_REG_REBALANCE_ON_CTX_SW

           ORR        x13, x13, x13

           ORR        x14, x14, x14

           ORR        x15, x15, x15

           ORR        x16, x16, x16

           ORR        x17, x17, x17

           ORR        x18, x18, x18

           ORR        x19, x19, x19

           ORR        x20, x20, x20

           ORR        x21, x21, x21

           MOV        V0.16B, V0.16B

           MOV        V1.16B, V1.16B

           MOV        V2.16B, V2.16B

           MOV        V3.16B, V3.16B

           MOV        V4.16B, V4.16B

           MOV        V5.16B, V5.16B

           MOV        V6.16B, V6.16B

           MOV        V7.16B, V7.16B

           MOV        V8.16B, V8.16B

           MOV        V9.16B, V9.16B

           MOV        V10.16B, V10.16B

           MOV        V11.16B, V11.16B

           MOV        V12.16B, V12.16B

           MOV        V13.16B, V13.16B

           MOV        V14.16B, V14.16B

           MOV        V15.16B, V15.16B

#endif

	mov	sp, x9

	ret

ENDPROC(cpu_switch_to)