Loading arch/arm/common/gic.c +0 −14 Original line number Diff line number Diff line Loading @@ -67,25 +67,11 @@ static inline unsigned int gic_irq(unsigned int irq) /* * Routines to acknowledge, disable and enable interrupts * * Linux assumes that when we're done with an interrupt we need to * unmask it, in the same way we need to unmask an interrupt when * we first enable it. * * The GIC has a separate notion of "end of interrupt" to re-enable * an interrupt after handling, in order to support hardware * prioritisation. * * We can make the GIC behave in the way that Linux expects by making * our "acknowledge" routine disable the interrupt, then mark it as * complete. */ static void gic_ack_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); spin_lock(&irq_controller_lock); writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4); writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI); spin_unlock(&irq_controller_lock); } Loading Loading
arch/arm/common/gic.c +0 −14 Original line number Diff line number Diff line Loading @@ -67,25 +67,11 @@ static inline unsigned int gic_irq(unsigned int irq) /* * Routines to acknowledge, disable and enable interrupts * * Linux assumes that when we're done with an interrupt we need to * unmask it, in the same way we need to unmask an interrupt when * we first enable it. * * The GIC has a separate notion of "end of interrupt" to re-enable * an interrupt after handling, in order to support hardware * prioritisation. * * We can make the GIC behave in the way that Linux expects by making * our "acknowledge" routine disable the interrupt, then mark it as * complete. */ static void gic_ack_irq(unsigned int irq) { u32 mask = 1 << (irq % 32); spin_lock(&irq_controller_lock); writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4); writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI); spin_unlock(&irq_controller_lock); } Loading