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Commit 4f8a6b1a authored by Stephane Eranian's avatar Stephane Eranian Committed by Thomas Gleixner
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i386: i386 add AMD64 Barcelona PMU MSR definitions to msr.h 



[i386] add AMD Barcelona PMU MSR definitions

AK: Not used right now, but will presumably at some point.

[ tglx: arch/x86 adaptation ]

Signed-off-by: default avatarStephane Eranian <eranian@hpl.hp.com>
Signed-off-by: default avatarRobert Richter <robert.richter@amd.com>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 54ef3400

include/asm-x86/msr-index.h

+25 −11
Original line number Diff line number Diff line
@@ -73,8 +73,32 @@ 
#define MSR_P6_EVNTSEL0			0x00000186

#define MSR_P6_EVNTSEL1			0x00000187



/* K7/K8 MSRs. Not complete. See the architecture manual for a more

/* AMD64 MSRs. Not complete. See the architecture manual for a more

   complete list. */



#define MSR_AMD64_IBSFETCHCTL		0xc0011030

#define MSR_AMD64_IBSFETCHLINAD		0xc0011031

#define MSR_AMD64_IBSFETCHPHYSAD	0xc0011032

#define MSR_AMD64_IBSOPCTL		0xc0011033

#define MSR_AMD64_IBSOPRIP		0xc0011034

#define MSR_AMD64_IBSOPDATA		0xc0011035

#define MSR_AMD64_IBSOPDATA2		0xc0011036

#define MSR_AMD64_IBSOPDATA3		0xc0011037

#define MSR_AMD64_IBSDCLINAD		0xc0011038

#define MSR_AMD64_IBSDCPHYSAD		0xc0011039

#define MSR_AMD64_IBSCTL		0xc001103a



/* K8 MSRs */

#define MSR_K8_TOP_MEM1			0xc001001a

#define MSR_K8_TOP_MEM2			0xc001001d

#define MSR_K8_SYSCFG			0xc0010010

#define MSR_K8_HWCR			0xc0010015

#define MSR_K8_ENABLE_C1E		0xc0010055

#define K8_MTRRFIXRANGE_DRAM_ENABLE	0x00040000 /* MtrrFixDramEn bit    */

#define K8_MTRRFIXRANGE_DRAM_MODIFY	0x00080000 /* MtrrFixDramModEn bit */

#define K8_MTRR_RDMEM_WRMEM_MASK	0x18181818 /* Mask: RdMem|WrMem    */



/* K7 MSRs */

#define MSR_K7_EVNTSEL0			0xc0010000

#define MSR_K7_PERFCTR0			0xc0010004

#define MSR_K7_EVNTSEL1			0xc0010001
@@ -83,20 +107,10 @@ 
#define MSR_K7_PERFCTR2			0xc0010006

#define MSR_K7_EVNTSEL3			0xc0010003

#define MSR_K7_PERFCTR3			0xc0010007

#define MSR_K8_TOP_MEM1			0xc001001a

#define MSR_K7_CLK_CTL			0xc001001b

#define MSR_K8_TOP_MEM2			0xc001001d

#define MSR_K8_SYSCFG			0xc0010010



#define K8_MTRRFIXRANGE_DRAM_ENABLE	0x00040000 /* MtrrFixDramEn bit    */

#define K8_MTRRFIXRANGE_DRAM_MODIFY	0x00080000 /* MtrrFixDramModEn bit */

#define K8_MTRR_RDMEM_WRMEM_MASK	0x18181818 /* Mask: RdMem|WrMem    */



#define MSR_K7_HWCR			0xc0010015

#define MSR_K8_HWCR			0xc0010015

#define MSR_K7_FID_VID_CTL		0xc0010041

#define MSR_K7_FID_VID_STATUS		0xc0010042

#define MSR_K8_ENABLE_C1E		0xc0010055



/* K6 MSRs */

#define MSR_K6_EFER			0xc0000080