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Commit 4d022604 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge branch 'pm-upstream/pm-off' of... 

Merge branch 'pm-upstream/pm-off' of ssh://master.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into 7xx-iosplit-plat-merge
parents 774facda f265dc4c

arch/arm/mach-omap2/control.c

+381 −0
Original line number Diff line number Diff line
@@ -17,9 +17,125 @@ 


#include <plat/common.h>

#include <plat/control.h>

#include <plat/sdrc.h>

#include "cm-regbits-34xx.h"

#include "prm-regbits-34xx.h"

#include "cm.h"

#include "prm.h"

#include "sdrc.h"



static void __iomem *omap2_ctrl_base;



#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)

struct omap3_scratchpad {

	u32 boot_config_ptr;

	u32 public_restore_ptr;

	u32 secure_ram_restore_ptr;

	u32 sdrc_module_semaphore;

	u32 prcm_block_offset;

	u32 sdrc_block_offset;

};



struct omap3_scratchpad_prcm_block {

	u32 prm_clksrc_ctrl;

	u32 prm_clksel;

	u32 cm_clksel_core;

	u32 cm_clksel_wkup;

	u32 cm_clken_pll;

	u32 cm_autoidle_pll;

	u32 cm_clksel1_pll;

	u32 cm_clksel2_pll;

	u32 cm_clksel3_pll;

	u32 cm_clken_pll_mpu;

	u32 cm_autoidle_pll_mpu;

	u32 cm_clksel1_pll_mpu;

	u32 cm_clksel2_pll_mpu;

	u32 prcm_block_size;

};



struct omap3_scratchpad_sdrc_block {

	u16 sysconfig;

	u16 cs_cfg;

	u16 sharing;

	u16 err_type;

	u32 dll_a_ctrl;

	u32 dll_b_ctrl;

	u32 power;

	u32 cs_0;

	u32 mcfg_0;

	u16 mr_0;

	u16 emr_1_0;

	u16 emr_2_0;

	u16 emr_3_0;

	u32 actim_ctrla_0;

	u32 actim_ctrlb_0;

	u32 rfr_ctrl_0;

	u32 cs_1;

	u32 mcfg_1;

	u16 mr_1;

	u16 emr_1_1;

	u16 emr_2_1;

	u16 emr_3_1;

	u32 actim_ctrla_1;

	u32 actim_ctrlb_1;

	u32 rfr_ctrl_1;

	u16 dcdl_1_ctrl;

	u16 dcdl_2_ctrl;

	u32 flags;

	u32 block_size;

};



void *omap3_secure_ram_storage;



/*

 * This is used to store ARM registers in SDRAM before attempting

 * an MPU OFF. The save and restore happens from the SRAM sleep code.

 * The address is stored in scratchpad, so that it can be used

 * during the restore path.

 */

u32 omap3_arm_context[128];



struct omap3_control_regs {

	u32 sysconfig;

	u32 devconf0;

	u32 mem_dftrw0;

	u32 mem_dftrw1;

	u32 msuspendmux_0;

	u32 msuspendmux_1;

	u32 msuspendmux_2;

	u32 msuspendmux_3;

	u32 msuspendmux_4;

	u32 msuspendmux_5;

	u32 sec_ctrl;

	u32 devconf1;

	u32 csirxfe;

	u32 iva2_bootaddr;

	u32 iva2_bootmod;

	u32 debobs_0;

	u32 debobs_1;

	u32 debobs_2;

	u32 debobs_3;

	u32 debobs_4;

	u32 debobs_5;

	u32 debobs_6;

	u32 debobs_7;

	u32 debobs_8;

	u32 prog_io0;

	u32 prog_io1;

	u32 dss_dpll_spreading;

	u32 core_dpll_spreading;

	u32 per_dpll_spreading;

	u32 usbhost_dpll_spreading;

	u32 pbias_lite;

	u32 temp_sensor;

	u32 sramldo4;

	u32 sramldo5;

	u32 csi;

};



static struct omap3_control_regs control_context;

#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */



#define OMAP_CTRL_REGADDR(reg)		(omap2_ctrl_base + (reg))



void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
@@ -62,3 +178,268 @@ void omap_ctrl_writel(u32 val, u16 offset) 
	__raw_writel(val, OMAP_CTRL_REGADDR(offset));

}



#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)

/*

 * Clears the scratchpad contents in case of cold boot-

 * called during bootup

 */

void omap3_clear_scratchpad_contents(void)

{

	u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;

	u32 *v_addr;

	u32 offset = 0;

	v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);

	if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &

		OMAP3430_GLOBAL_COLD_RST) {

		for ( ; offset <= max_offset; offset += 0x4)

			__raw_writel(0x0, (v_addr + offset));

		prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,

			OMAP3_PRM_RSTST_OFFSET);

	}

}



/* Populate the scratchpad structure with restore structure */

void omap3_save_scratchpad_contents(void)

{

	void * __iomem scratchpad_address;

	u32 arm_context_addr;

	struct omap3_scratchpad scratchpad_contents;

	struct omap3_scratchpad_prcm_block prcm_block_contents;

	struct omap3_scratchpad_sdrc_block sdrc_block_contents;



	/* Populate the Scratchpad contents */

	scratchpad_contents.boot_config_ptr = 0x0;

	if (omap_rev() != OMAP3430_REV_ES3_0 &&

					omap_rev() != OMAP3430_REV_ES3_1)

		scratchpad_contents.public_restore_ptr =

			virt_to_phys(get_restore_pointer());

	else

		scratchpad_contents.public_restore_ptr =

			virt_to_phys(get_es3_restore_pointer());

	if (omap_type() == OMAP2_DEVICE_TYPE_GP)

		scratchpad_contents.secure_ram_restore_ptr = 0x0;

	else

		scratchpad_contents.secure_ram_restore_ptr =

			(u32) __pa(omap3_secure_ram_storage);

	scratchpad_contents.sdrc_module_semaphore = 0x0;

	scratchpad_contents.prcm_block_offset = 0x2C;

	scratchpad_contents.sdrc_block_offset = 0x64;



	/* Populate the PRCM block contents */

	prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,

			OMAP3_PRM_CLKSRC_CTRL_OFFSET);

	prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,

			OMAP3_PRM_CLKSEL_OFFSET);

	prcm_block_contents.cm_clksel_core =

			cm_read_mod_reg(CORE_MOD, CM_CLKSEL);

	prcm_block_contents.cm_clksel_wkup =

			cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);

	prcm_block_contents.cm_clken_pll =

			cm_read_mod_reg(PLL_MOD, CM_CLKEN);

	prcm_block_contents.cm_autoidle_pll =

			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);

	prcm_block_contents.cm_clksel1_pll =

			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);

	prcm_block_contents.cm_clksel2_pll =

			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);

	prcm_block_contents.cm_clksel3_pll =

			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);

	prcm_block_contents.cm_clken_pll_mpu =

			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);

	prcm_block_contents.cm_autoidle_pll_mpu =

			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);

	prcm_block_contents.cm_clksel1_pll_mpu =

			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);

	prcm_block_contents.cm_clksel2_pll_mpu =

			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);

	prcm_block_contents.prcm_block_size = 0x0;



	/* Populate the SDRC block contents */

	sdrc_block_contents.sysconfig =

			(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);

	sdrc_block_contents.cs_cfg =

			(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);

	sdrc_block_contents.sharing =

			(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);

	sdrc_block_contents.err_type =

			(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);

	sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);

	sdrc_block_contents.dll_b_ctrl = 0x0;

	/*

	 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should

	 * be programed to issue automatic self refresh on timeout

	 * of AUTO_CNT = 1 prior to any transition to OFF mode.

	 */

	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)

			&& (omap_rev() >= OMAP3430_REV_ES3_0))

		sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &

				~(SDRC_POWER_AUTOCOUNT_MASK|

				SDRC_POWER_CLKCTRL_MASK)) |

				(1 << SDRC_POWER_AUTOCOUNT_SHIFT) |

				SDRC_SELF_REFRESH_ON_AUTOCOUNT;

	else

		sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);



	sdrc_block_contents.cs_0 = 0x0;

	sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);

	sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);

	sdrc_block_contents.emr_1_0 = 0x0;

	sdrc_block_contents.emr_2_0 = 0x0;

	sdrc_block_contents.emr_3_0 = 0x0;

	sdrc_block_contents.actim_ctrla_0 =

			sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);

	sdrc_block_contents.actim_ctrlb_0 =

			sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);

	sdrc_block_contents.rfr_ctrl_0 =

			sdrc_read_reg(SDRC_RFR_CTRL_0);

	sdrc_block_contents.cs_1 = 0x0;

	sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);

	sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;

	sdrc_block_contents.emr_1_1 = 0x0;

	sdrc_block_contents.emr_2_1 = 0x0;

	sdrc_block_contents.emr_3_1 = 0x0;

	sdrc_block_contents.actim_ctrla_1 =

			sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);

	sdrc_block_contents.actim_ctrlb_1 =

			sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);

	sdrc_block_contents.rfr_ctrl_1 =

			sdrc_read_reg(SDRC_RFR_CTRL_1);

	sdrc_block_contents.dcdl_1_ctrl = 0x0;

	sdrc_block_contents.dcdl_2_ctrl = 0x0;

	sdrc_block_contents.flags = 0x0;

	sdrc_block_contents.block_size = 0x0;



	arm_context_addr = virt_to_phys(omap3_arm_context);



	/* Copy all the contents to the scratchpad location */

	scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);

	memcpy_toio(scratchpad_address, &scratchpad_contents,

		 sizeof(scratchpad_contents));

	/* Scratchpad contents being 32 bits, a divide by 4 done here */

	memcpy_toio(scratchpad_address +

		scratchpad_contents.prcm_block_offset,

		&prcm_block_contents, sizeof(prcm_block_contents));

	memcpy_toio(scratchpad_address +

		scratchpad_contents.sdrc_block_offset,

		&sdrc_block_contents, sizeof(sdrc_block_contents));

	/*

	 * Copies the address of the location in SDRAM where ARM

	 * registers get saved during a MPU OFF transition.

	 */

	memcpy_toio(scratchpad_address +

		scratchpad_contents.sdrc_block_offset +

		sizeof(sdrc_block_contents), &arm_context_addr, 4);

}



void omap3_control_save_context(void)

{

	control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);

	control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);

	control_context.mem_dftrw0 =

			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);

	control_context.mem_dftrw1 =

			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);

	control_context.msuspendmux_0 =

			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);

	control_context.msuspendmux_1 =

			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);

	control_context.msuspendmux_2 =

			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);

	control_context.msuspendmux_3 =

			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);

	control_context.msuspendmux_4 =

			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);

	control_context.msuspendmux_5 =

			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);

	control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);

	control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);

	control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);

	control_context.iva2_bootaddr =

			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);

	control_context.iva2_bootmod =

			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);

	control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));

	control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));

	control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));

	control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));

	control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));

	control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));

	control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));

	control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));

	control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));

	control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);

	control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);

	control_context.dss_dpll_spreading =

			omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);

	control_context.core_dpll_spreading =

			omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);

	control_context.per_dpll_spreading =

			omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);

	control_context.usbhost_dpll_spreading =

		omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);

	control_context.pbias_lite =

			omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);

	control_context.temp_sensor =

			omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);

	control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);

	control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);

	control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);

	return;

}



void omap3_control_restore_context(void)

{

	omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);

	omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);

	omap_ctrl_writel(control_context.mem_dftrw0,

					OMAP343X_CONTROL_MEM_DFTRW0);

	omap_ctrl_writel(control_context.mem_dftrw1,

					OMAP343X_CONTROL_MEM_DFTRW1);

	omap_ctrl_writel(control_context.msuspendmux_0,

					OMAP2_CONTROL_MSUSPENDMUX_0);

	omap_ctrl_writel(control_context.msuspendmux_1,

					OMAP2_CONTROL_MSUSPENDMUX_1);

	omap_ctrl_writel(control_context.msuspendmux_2,

					OMAP2_CONTROL_MSUSPENDMUX_2);

	omap_ctrl_writel(control_context.msuspendmux_3,

					OMAP2_CONTROL_MSUSPENDMUX_3);

	omap_ctrl_writel(control_context.msuspendmux_4,

					OMAP2_CONTROL_MSUSPENDMUX_4);

	omap_ctrl_writel(control_context.msuspendmux_5,

					OMAP2_CONTROL_MSUSPENDMUX_5);

	omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);

	omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);

	omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);

	omap_ctrl_writel(control_context.iva2_bootaddr,

					OMAP343X_CONTROL_IVA2_BOOTADDR);

	omap_ctrl_writel(control_context.iva2_bootmod,

					OMAP343X_CONTROL_IVA2_BOOTMOD);

	omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));

	omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));

	omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));

	omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));

	omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));

	omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));

	omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));

	omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));

	omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));

	omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);

	omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);

	omap_ctrl_writel(control_context.dss_dpll_spreading,

					OMAP343X_CONTROL_DSS_DPLL_SPREADING);

	omap_ctrl_writel(control_context.core_dpll_spreading,

					OMAP343X_CONTROL_CORE_DPLL_SPREADING);

	omap_ctrl_writel(control_context.per_dpll_spreading,

					OMAP343X_CONTROL_PER_DPLL_SPREADING);

	omap_ctrl_writel(control_context.usbhost_dpll_spreading,

				OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);

	omap_ctrl_writel(control_context.pbias_lite,

					OMAP343X_CONTROL_PBIAS_LITE);

	omap_ctrl_writel(control_context.temp_sensor,

					OMAP343X_CONTROL_TEMP_SENSOR);

	omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);

	omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);

	omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);

	return;

}

#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */

arch/arm/mach-omap2/gpmc.c

+95 −3
Original line number Diff line number Diff line
@@ -62,6 +62,33 @@ 
#define ENABLE_PREFETCH		(0x1 << 7)

#define DMA_MPU_MODE		2



/* Structure to save gpmc cs context */

struct gpmc_cs_config {

	u32 config1;

	u32 config2;

	u32 config3;

	u32 config4;

	u32 config5;

	u32 config6;

	u32 config7;

	int is_valid;

};



/*

 * Structure to save/restore gpmc context

 * to support core off on OMAP3

 */

struct omap3_gpmc_regs {

	u32 sysconfig;

	u32 irqenable;

	u32 timeout_ctrl;

	u32 config;

	u32 prefetch_config1;

	u32 prefetch_config2;

	u32 prefetch_control;

	struct gpmc_cs_config cs_context[GPMC_CS_NUM];

};



static struct resource	gpmc_mem_root;

static struct resource	gpmc_cs_mem[GPMC_CS_NUM];

static DEFINE_SPINLOCK(gpmc_mem_lock);
@@ -261,7 +288,7 @@ static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) 
	l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;

	l &= ~(0x0f << 8);

	l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;

	l |= 1 << 6;		/* CSVALID */

	l |= GPMC_CONFIG7_CSVALID;

	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);

}
@@ -270,7 +297,7 @@ static void gpmc_cs_disable_mem(int cs) 
	u32 l;



	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);

	l &= ~(1 << 6);		/* CSVALID */

	l &= ~GPMC_CONFIG7_CSVALID;

	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);

}
@@ -290,7 +317,7 @@ static int gpmc_cs_mem_enabled(int cs) 
	u32 l;



	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);

	return l & (1 << 6);

	return l & GPMC_CONFIG7_CSVALID;

}



int gpmc_cs_set_reserved(int cs, int reserved)
@@ -516,3 +543,68 @@ void __init gpmc_init(void) 
	gpmc_write_reg(GPMC_SYSCONFIG, l);

	gpmc_mem_init();

}



#ifdef CONFIG_ARCH_OMAP3

static struct omap3_gpmc_regs gpmc_context;



void omap3_gpmc_save_context()

{

	int i;

	gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);

	gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);

	gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);

	gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);

	gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);

	gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);

	gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);

	for (i = 0; i < GPMC_CS_NUM; i++) {

		gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);

		if (gpmc_context.cs_context[i].is_valid) {

			gpmc_context.cs_context[i].config1 =

				gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);

			gpmc_context.cs_context[i].config2 =

				gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);

			gpmc_context.cs_context[i].config3 =

				gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);

			gpmc_context.cs_context[i].config4 =

				gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);

			gpmc_context.cs_context[i].config5 =

				gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);

			gpmc_context.cs_context[i].config6 =

				gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);

			gpmc_context.cs_context[i].config7 =

				gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);

		}

	}

}



void omap3_gpmc_restore_context()

{

	int i;

	gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);

	gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);

	gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);

	gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);

	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);

	gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);

	gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);

	for (i = 0; i < GPMC_CS_NUM; i++) {

		if (gpmc_context.cs_context[i].is_valid) {

			gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,

				gpmc_context.cs_context[i].config1);

			gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,

				gpmc_context.cs_context[i].config2);

			gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,

				gpmc_context.cs_context[i].config3);

			gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,

				gpmc_context.cs_context[i].config4);

			gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,

				gpmc_context.cs_context[i].config5);

			gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,

				gpmc_context.cs_context[i].config6);

			gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,

				gpmc_context.cs_context[i].config7);

		}

	}

}

#endif /* CONFIG_ARCH_OMAP3 */

arch/arm/mach-omap2/irq.c

+66 −0
Original line number Diff line number Diff line
@@ -25,6 +25,10 @@ 
#define INTC_SYSSTATUS		0x0014

#define INTC_SIR		0x0040

#define INTC_CONTROL		0x0048

#define INTC_PROTECTION		0x004C

#define INTC_IDLE		0x0050

#define INTC_THRESHOLD		0x0068

#define INTC_MIR0		0x0084

#define INTC_MIR_CLEAR0		0x0088

#define INTC_MIR_SET0		0x008c

#define INTC_PENDING_IRQ0	0x0098
@@ -48,6 +52,18 @@ static struct omap_irq_bank { 
	},

};



/* Structure to save interrupt controller context */

struct omap3_intc_regs {

	u32 sysconfig;

	u32 protection;

	u32 idle;

	u32 threshold;

	u32 ilr[INTCPS_NR_IRQS];

	u32 mir[INTCPS_NR_MIR_REGS];

};



static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];



/* INTC bank register get/set */



static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
@@ -209,3 +225,53 @@ void __init omap_init_irq(void) 
	}

}



#ifdef CONFIG_ARCH_OMAP3

void omap_intc_save_context(void)

{

	int ind = 0, i = 0;

	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {

		struct omap_irq_bank *bank = irq_banks + ind;

		intc_context[ind].sysconfig =

			intc_bank_read_reg(bank, INTC_SYSCONFIG);

		intc_context[ind].protection =

			intc_bank_read_reg(bank, INTC_PROTECTION);

		intc_context[ind].idle =

			intc_bank_read_reg(bank, INTC_IDLE);

		intc_context[ind].threshold =

			intc_bank_read_reg(bank, INTC_THRESHOLD);

		for (i = 0; i < INTCPS_NR_IRQS; i++)

			intc_context[ind].ilr[i] =

				intc_bank_read_reg(bank, (0x100 + 0x4*i));

		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)

			intc_context[ind].mir[i] =

				intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +

				(0x20 * i));

	}

}



void omap_intc_restore_context(void)

{

	int ind = 0, i = 0;



	for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {

		struct omap_irq_bank *bank = irq_banks + ind;

		intc_bank_write_reg(intc_context[ind].sysconfig,

					bank, INTC_SYSCONFIG);

		intc_bank_write_reg(intc_context[ind].sysconfig,

					bank, INTC_SYSCONFIG);

		intc_bank_write_reg(intc_context[ind].protection,

					bank, INTC_PROTECTION);

		intc_bank_write_reg(intc_context[ind].idle,

					bank, INTC_IDLE);

		intc_bank_write_reg(intc_context[ind].threshold,

					bank, INTC_THRESHOLD);

		for (i = 0; i < INTCPS_NR_IRQS; i++)

			intc_bank_write_reg(intc_context[ind].ilr[i],

				bank, (0x100 + 0x4*i));

		for (i = 0; i < INTCPS_NR_MIR_REGS; i++)

			intc_bank_write_reg(intc_context[ind].mir[i],

				 &irq_banks[0], INTC_MIR0 + (0x20 * i));

	}

	/* MIRs are saved and restore with other PRCM registers */

}

#endif /* CONFIG_ARCH_OMAP3 */

arch/arm/mach-omap2/pm-debug.c

+29 −0
Original line number Diff line number Diff line
@@ -527,6 +527,29 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir) 
	return 0;

}



static int option_get(void *data, u64 *val)

{

	u32 *option = data;



	*val = *option;



	return 0;

}



static int option_set(void *data, u64 val)

{

	u32 *option = data;



	*option = val;



	if (option == &enable_off_mode)

		omap3_pm_off_mode_enable(val);



	return 0;

}



DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");



static int __init pm_dbg_init(void)

{

	int i;
@@ -569,6 +592,12 @@ static int __init pm_dbg_init(void) 


		}



	(void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,

				   &enable_off_mode, &pm_dbg_option_fops);

	(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,

				   &sleep_while_idle, &pm_dbg_option_fops);

	(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,

				   &wakeup_timer_seconds, &pm_dbg_option_fops);

	pm_dbg_init_done = 1;



	return 0;

arch/arm/mach-omap2/pm.h

+10 −0
Original line number Diff line number Diff line
@@ -13,9 +13,18 @@ 


#include <plat/powerdomain.h>



extern u32 enable_off_mode;

extern u32 sleep_while_idle;



extern void *omap3_secure_ram_storage;

extern void omap3_pm_off_mode_enable(int);



extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);

extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);



extern u32 wakeup_timer_seconds;

extern struct omap_dm_timer *gptimer_wakeup;



#ifdef CONFIG_PM_DEBUG

extern void omap2_pm_dump(int mode, int resume, unsigned int us);

extern int omap2_pm_debug;
@@ -36,6 +45,7 @@ extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl, 
					void __iomem *sdrc_power);

extern void omap34xx_cpu_suspend(u32 *addr, int save_state);

extern void save_secure_ram_context(u32 *addr);

extern void omap3_save_scratchpad_contents(void);



extern unsigned int omap24xx_idle_loop_suspend_sz;

extern unsigned int omap34xx_suspend_sz;