Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4c609cb8 authored by Jesse Barnes's avatar Jesse Barnes Committed by Keith Packard
Browse files

drm/i915: PLL macro cleanup and pipe assertion check 



Add a macro for accessing the two pipe PLLs and add a check to make sure
we don't access a non-existent one in the enable/disable functions.

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Tested-By: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-By: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent c4f9c4c2

drivers/gpu/drm/i915/i915_reg.h

+3 −3
Original line number Original line Diff line number Diff line
@@ -2967,15 +2967,15 @@ 




#define _PCH_DPLL_A              0xc6014

#define _PCH_DPLL_A              0xc6014

#define _PCH_DPLL_B              0xc6018

#define _PCH_DPLL_B              0xc6018

#define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)

#define PCH_DPLL(pipe) (pipe == 0 ?  _PCH_DPLL_A : _PCH_DPLL_B)





#define _PCH_FPA0                0xc6040

#define _PCH_FPA0                0xc6040

#define  FP_CB_TUNE		(0x3<<22)

#define  FP_CB_TUNE		(0x3<<22)

#define _PCH_FPA1                0xc6044

#define _PCH_FPA1                0xc6044

#define _PCH_FPB0                0xc6048

#define _PCH_FPB0                0xc6048

#define _PCH_FPB1                0xc604c

#define _PCH_FPB1                0xc604c

#define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)

#define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0)

#define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)

#define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1)





#define PCH_DPLL_TEST           0xc606c

#define PCH_DPLL_TEST           0xc606c

drivers/gpu/drm/i915/intel_display.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -1172,6 +1172,9 @@ static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, 
	int reg;

	int reg;

	u32 val;

	u32 val;





	if (pipe > 1)

		return;



	/* PCH only available on ILK+ */

	/* PCH only available on ILK+ */

	BUG_ON(dev_priv->info->gen < 5);

	BUG_ON(dev_priv->info->gen < 5);
@@ -1192,6 +1195,9 @@ static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, 
	int reg;

	int reg;

	u32 val;

	u32 val;





	if (pipe > 1)

		return;



	/* PCH only available on ILK+ */

	/* PCH only available on ILK+ */

	BUG_ON(dev_priv->info->gen < 5);

	BUG_ON(dev_priv->info->gen < 5);