Commit 4c552a5b authored Feb 18, 2014 by andrea merello Committed by John W. Linville Mar 04, 2014

rtl818x: Make sure the TX descriptor "valid" flag is written by last



The TX descriptors are consumed by the HW using DMA.
Even if in the driver code the memory write that sets the "valid"
flag appears after all other writes, the CPU may reorder writes,
causing the HW to consider as valid a not-fully-written yet
descriptor.

This may cause HW incorrect behaviour.

This can happen because (AFAIK) the HW may attempt DMA
asynchronously without waiting to be kicked by the following
register write.

This patch adds a write memory barrier to enforce writes ordering.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

parent f3b6a488

drivers/net/wireless/rtl818x/rtl8180/dev.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -335,6 +335,11 @@ static void rtl8180_tx(struct ieee80211_hw *dev,
		entry->flags2 = info->control.rates[1].idx >= 0 ?
		ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
		entry->retry_limit = info->control.rates[0].count;

		/* We must be sure that tx_flags is written last because the HW
		* looks at it to check if the rest of data is valid or not
		*/
		wmb();
		entry->flags = cpu_to_le32(tx_flags);
		__skb_queue_tail(&ring->queue, skb);
		if (ring->entries - skb_queue_len(&ring->queue) < 2)