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Commit 4c3cc72c authored by Tomasz Figa's avatar Tomasz Figa Committed by Kukjin Kim
Browse files

clk: exynos4: Add missing mout_mipihsi clock 



This patch adds missing output of mux MIPIHSI which is needed for
div_mipihsi clock.

Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Acked-by: default avatarMike Turquette <mturquette@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 74f7f8ba

drivers/clk/samsung/clk-exynos4.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -381,6 +381,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 
	MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),

	MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),

	MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),

	MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),

	MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),

	MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),

	MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),

	MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),

	MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),

	MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),

	MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),

	MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),

	MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),