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Commit 4bc22a1a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-radeon-next' of ../drm-radeon-next into drm-core-next 

* 'drm-radeon-next' of ../drm-radeon-next:
  drm/radeon: introduce a sub allocator and convert ib pool to it v4
  drm/radeon/kms: add support for per-ring fence interrupts
  drm/radeon/kms: add cayman specific fence_ring_emit
  drm/radeon/kms: add some new ring params to better handle other ring types
  drm/radeon: improve radeon_test_syncing function
  drm/radeon: precompute fence cpu/gpu addr once v3
  drm/radeon: move ring debugfs into radeon_ring.c
  drm/radeon: rename struct radeon_cp to radeon_ring
  drm/radeon: disable compute rings on cayman for now
  drm/radeon: add radeon_fence_count_emited function
  drm/radeon: make some asic pointers per ring
  drm/radeon: Add radeon_test_syncing function v2
  drm/radeon: make cp variable an array
  drm/radeon: make ring rptr and wptr register offsets variable
  drm/radeon: make all functions work with multiple rings.
  drm/radeon/kms: add support for semaphores v3
  drm/radeon/kms: add support for multiple fence queues v2
  drm/radeon: fix a spelling mistake
  drm/radeon: no need to check all relocs for duplicates
  drm/radeon: fix debugfs handling v3
parents e2e022ec b15ba512

drivers/gpu/drm/radeon/Makefile

+3 −2
Original line number Diff line number Diff line
@@ -70,7 +70,8 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \

	r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \

	evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \

	radeon_trace_points.o ni.o cayman_blit_shaders.o atombios_encoders.o

	radeon_trace_points.o ni.o cayman_blit_shaders.o atombios_encoders.o \

	radeon_semaphore.o radeon_sa.o



radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

drivers/gpu/drm/radeon/evergreen.c

+148 −86
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ 
static void evergreen_gpu_init(struct radeon_device *rdev);

void evergreen_fini(struct radeon_device *rdev);

void evergreen_pcie_gen2_enable(struct radeon_device *rdev);

extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,

				     int ring, u32 cp_int_cntl);



void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)

{
@@ -1311,18 +1313,20 @@ void evergreen_mc_program(struct radeon_device *rdev) 
 */

void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)

{

	struct radeon_ring *ring = &rdev->ring[ib->fence->ring];



	/* set to DX10/11 mode */

	radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));

	radeon_ring_write(rdev, 1);

	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));

	radeon_ring_write(ring, 1);

	/* FIXME: implement */

	radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

	radeon_ring_write(rdev,

	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

	radeon_ring_write(ring,

#ifdef __BIG_ENDIAN

			  (2 << 0) |

#endif

			  (ib->gpu_addr & 0xFFFFFFFC));

	radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);

	radeon_ring_write(rdev, ib->length_dw);

	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);

	radeon_ring_write(ring, ib->length_dw);

}
@@ -1360,71 +1364,73 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev) 


static int evergreen_cp_start(struct radeon_device *rdev)

{

	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	int r, i;

	uint32_t cp_me;



	r = radeon_ring_lock(rdev, 7);

	r = radeon_ring_lock(rdev, ring, 7);

	if (r) {

		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);

		return r;

	}

	radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));

	radeon_ring_write(rdev, 0x1);

	radeon_ring_write(rdev, 0x0);

	radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);

	radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));

	radeon_ring_write(rdev, 0);

	radeon_ring_write(rdev, 0);

	radeon_ring_unlock_commit(rdev);

	radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));

	radeon_ring_write(ring, 0x1);

	radeon_ring_write(ring, 0x0);

	radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);

	radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));

	radeon_ring_write(ring, 0);

	radeon_ring_write(ring, 0);

	radeon_ring_unlock_commit(rdev, ring);



	cp_me = 0xff;

	WREG32(CP_ME_CNTL, cp_me);



	r = radeon_ring_lock(rdev, evergreen_default_size + 19);

	r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);

	if (r) {

		DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);

		return r;

	}



	/* setup clear context state */

	radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

	radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);

	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

	radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);



	for (i = 0; i < evergreen_default_size; i++)

		radeon_ring_write(rdev, evergreen_default_state[i]);

		radeon_ring_write(ring, evergreen_default_state[i]);



	radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

	radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);

	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

	radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);



	/* set clear context state */

	radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));

	radeon_ring_write(rdev, 0);

	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

	radeon_ring_write(ring, 0);



	/* SQ_VTX_BASE_VTX_LOC */

	radeon_ring_write(rdev, 0xc0026f00);

	radeon_ring_write(rdev, 0x00000000);

	radeon_ring_write(rdev, 0x00000000);

	radeon_ring_write(rdev, 0x00000000);

	radeon_ring_write(ring, 0xc0026f00);

	radeon_ring_write(ring, 0x00000000);

	radeon_ring_write(ring, 0x00000000);

	radeon_ring_write(ring, 0x00000000);



	/* Clear consts */

	radeon_ring_write(rdev, 0xc0036f00);

	radeon_ring_write(rdev, 0x00000bc4);

	radeon_ring_write(rdev, 0xffffffff);

	radeon_ring_write(rdev, 0xffffffff);

	radeon_ring_write(rdev, 0xffffffff);

	radeon_ring_write(ring, 0xc0036f00);

	radeon_ring_write(ring, 0x00000bc4);

	radeon_ring_write(ring, 0xffffffff);

	radeon_ring_write(ring, 0xffffffff);

	radeon_ring_write(ring, 0xffffffff);



	radeon_ring_write(rdev, 0xc0026900);

	radeon_ring_write(rdev, 0x00000316);

	radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */

	radeon_ring_write(rdev, 0x00000010); /*  */

	radeon_ring_write(ring, 0xc0026900);

	radeon_ring_write(ring, 0x00000316);

	radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */

	radeon_ring_write(ring, 0x00000010); /*  */



	radeon_ring_unlock_commit(rdev);

	radeon_ring_unlock_commit(rdev, ring);



	return 0;

}



int evergreen_cp_resume(struct radeon_device *rdev)

{

	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	u32 tmp;

	u32 rb_bufsz;

	int r;
@@ -1442,13 +1448,13 @@ int evergreen_cp_resume(struct radeon_device *rdev) 
	RREG32(GRBM_SOFT_RESET);



	/* Set ring buffer size */

	rb_bufsz = drm_order(rdev->cp.ring_size / 8);

	rb_bufsz = drm_order(ring->ring_size / 8);

	tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;

#ifdef __BIG_ENDIAN

	tmp |= BUF_SWAP_32BIT;

#endif

	WREG32(CP_RB_CNTL, tmp);

	WREG32(CP_SEM_WAIT_TIMER, 0x4);

	WREG32(CP_SEM_WAIT_TIMER, 0x0);



	/* Set the write pointer delay */

	WREG32(CP_RB_WPTR_DELAY, 0);
@@ -1456,8 +1462,8 @@ int evergreen_cp_resume(struct radeon_device *rdev) 
	/* Initialize the ring buffer's read and write pointers */

	WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);

	WREG32(CP_RB_RPTR_WR, 0);

	rdev->cp.wptr = 0;

	WREG32(CP_RB_WPTR, rdev->cp.wptr);

	ring->wptr = 0;

	WREG32(CP_RB_WPTR, ring->wptr);



	/* set the wb address wether it's enabled or not */

	WREG32(CP_RB_RPTR_ADDR,
@@ -1475,16 +1481,16 @@ int evergreen_cp_resume(struct radeon_device *rdev) 
	mdelay(1);

	WREG32(CP_RB_CNTL, tmp);



	WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);

	WREG32(CP_RB_BASE, ring->gpu_addr >> 8);

	WREG32(CP_DEBUG, (1 << 27) | (1 << 28));



	rdev->cp.rptr = RREG32(CP_RB_RPTR);

	ring->rptr = RREG32(CP_RB_RPTR);



	evergreen_cp_start(rdev);

	rdev->cp.ready = true;

	r = radeon_ring_test(rdev);

	ring->ready = true;

	r = radeon_ring_test(rdev, ring);

	if (r) {

		rdev->cp.ready = false;

		ring->ready = false;

		return r;

	}

	return 0;
@@ -2353,7 +2359,7 @@ int evergreen_mc_init(struct radeon_device *rdev) 
	return 0;

}



bool evergreen_gpu_is_lockup(struct radeon_device *rdev)

bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)

{

	u32 srbm_status;

	u32 grbm_status;
@@ -2366,19 +2372,19 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev) 
	grbm_status_se0 = RREG32(GRBM_STATUS_SE0);

	grbm_status_se1 = RREG32(GRBM_STATUS_SE1);

	if (!(grbm_status & GUI_ACTIVE)) {

		r100_gpu_lockup_update(lockup, &rdev->cp);

		r100_gpu_lockup_update(lockup, ring);

		return false;

	}

	/* force CP activities */

	r = radeon_ring_lock(rdev, 2);

	r = radeon_ring_lock(rdev, ring, 2);

	if (!r) {

		/* PACKET2 NOP */

		radeon_ring_write(rdev, 0x80000000);

		radeon_ring_write(rdev, 0x80000000);

		radeon_ring_unlock_commit(rdev);

		radeon_ring_write(ring, 0x80000000);

		radeon_ring_write(ring, 0x80000000);

		radeon_ring_unlock_commit(rdev, ring);

	}

	rdev->cp.rptr = RREG32(CP_RB_RPTR);

	return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);

	ring->rptr = RREG32(CP_RB_RPTR);

	return r100_gpu_cp_is_lockup(rdev, lockup, ring);

}



static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
@@ -2470,6 +2476,12 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) 
{

	u32 tmp;



	if (rdev->family >= CHIP_CAYMAN) {

		cayman_cp_int_cntl_setup(rdev, 0,

					 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);

		cayman_cp_int_cntl_setup(rdev, 1, 0);

		cayman_cp_int_cntl_setup(rdev, 2, 0);

	} else

		WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);

	WREG32(GRBM_INT_CNTL, 0);

	WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
@@ -2515,6 +2527,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) 
int evergreen_irq_set(struct radeon_device *rdev)

{

	u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;

	u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;

	u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;

	u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;

	u32 grbm_int_cntl = 0;
@@ -2539,11 +2552,28 @@ int evergreen_irq_set(struct radeon_device *rdev) 
	hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;

	hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;



	if (rdev->irq.sw_int) {

		DRM_DEBUG("evergreen_irq_set: sw int\n");

	if (rdev->family >= CHIP_CAYMAN) {

		/* enable CP interrupts on all rings */

		if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {

			DRM_DEBUG("evergreen_irq_set: sw int gfx\n");

			cp_int_cntl |= TIME_STAMP_INT_ENABLE;

		}

		if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {

			DRM_DEBUG("evergreen_irq_set: sw int cp1\n");

			cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;

		}

		if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {

			DRM_DEBUG("evergreen_irq_set: sw int cp2\n");

			cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;

		}

	} else {

		if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {

			DRM_DEBUG("evergreen_irq_set: sw int gfx\n");

			cp_int_cntl |= RB_INT_ENABLE;

			cp_int_cntl |= TIME_STAMP_INT_ENABLE;

		}

	}



	if (rdev->irq.crtc_vblank_int[0] ||

	    rdev->irq.pflip[0]) {

		DRM_DEBUG("evergreen_irq_set: vblank 0\n");
@@ -2603,6 +2633,11 @@ int evergreen_irq_set(struct radeon_device *rdev) 
		grbm_int_cntl |= GUI_IDLE_INT_ENABLE;

	}



	if (rdev->family >= CHIP_CAYMAN) {

		cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);

		cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);

		cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);

	} else

		WREG32(CP_INT_CNTL, cp_int_cntl);

	WREG32(GRBM_INT_CNTL, grbm_int_cntl);
@@ -3018,11 +3053,24 @@ restart_ih: 
		case 177: /* CP_INT in IB1 */

		case 178: /* CP_INT in IB2 */

			DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);

			radeon_fence_process(rdev);

			radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);

			break;

		case 181: /* CP EOP event */

			DRM_DEBUG("IH: CP EOP\n");

			radeon_fence_process(rdev);

			if (rdev->family >= CHIP_CAYMAN) {

				switch (src_data) {

				case 0:

					radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);

					break;

				case 1:

					radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);

					break;

				case 2:

					radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);

					break;

				}

			} else

				radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);

			break;

		case 233: /* GUI IDLE */

			DRM_DEBUG("IH: GUI idle\n");
@@ -3052,6 +3100,7 @@ restart_ih: 


static int evergreen_startup(struct radeon_device *rdev)

{

	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

	int r;



	/* enable pcie gen2 link */
@@ -3106,6 +3155,12 @@ static int evergreen_startup(struct radeon_device *rdev) 
	if (r)

		return r;



	r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);

	if (r) {

		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);

		return r;

	}



	/* Enable IRQ */

	r = r600_irq_init(rdev);

	if (r) {
@@ -3115,7 +3170,9 @@ static int evergreen_startup(struct radeon_device *rdev) 
	}

	evergreen_irq_set(rdev);



	r = radeon_ring_init(rdev, rdev->cp.ring_size);

	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,

			     R600_CP_RB_RPTR, R600_CP_RB_WPTR,

			     0, 0xfffff, RADEON_CP_PACKET2);

	if (r)

		return r;

	r = evergreen_cp_load_microcode(rdev);
@@ -3125,6 +3182,17 @@ static int evergreen_startup(struct radeon_device *rdev) 
	if (r)

		return r;



	r = radeon_ib_pool_start(rdev);

	if (r)

		return r;



	r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);

	if (r) {

		DRM_ERROR("radeon: failed testing IB (%d).\n", r);

		rdev->accel_working = false;

		return r;

	}



	return 0;

}
@@ -3144,31 +3212,29 @@ int evergreen_resume(struct radeon_device *rdev) 
	/* post card */

	atom_asic_init(rdev->mode_info.atom_context);



	rdev->accel_working = true;

	r = evergreen_startup(rdev);

	if (r) {

		DRM_ERROR("evergreen startup failed on resume\n");

		return r;

	}



	r = r600_ib_test(rdev);

	if (r) {

		DRM_ERROR("radeon: failed testing IB (%d).\n", r);

		return r;

	}



	return r;



}



int evergreen_suspend(struct radeon_device *rdev)

{

	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];



	/* FIXME: we should wait for ring to be empty */

	radeon_ib_pool_suspend(rdev);

	r600_blit_suspend(rdev);

	r700_cp_stop(rdev);

	rdev->cp.ready = false;

	ring->ready = false;

	evergreen_irq_suspend(rdev);

	radeon_wb_disable(rdev);

	evergreen_pcie_gart_disable(rdev);

	r600_blit_suspend(rdev);



	return 0;

}
@@ -3243,8 +3309,8 @@ int evergreen_init(struct radeon_device *rdev) 
	if (r)

		return r;



	rdev->cp.ring_obj = NULL;

	r600_ring_init(rdev, 1024 * 1024);

	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;

	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);



	rdev->ih.ring_obj = NULL;

	r600_ih_ring_init(rdev, 64 * 1024);
@@ -3253,29 +3319,24 @@ int evergreen_init(struct radeon_device *rdev) 
	if (r)

		return r;



	r = radeon_ib_pool_init(rdev);

	rdev->accel_working = true;

	if (r) {

		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);

		rdev->accel_working = false;

	}



	r = evergreen_startup(rdev);

	if (r) {

		dev_err(rdev->dev, "disabling GPU acceleration\n");

		r700_cp_fini(rdev);

		r600_irq_fini(rdev);

		radeon_wb_fini(rdev);

		r100_ib_fini(rdev);

		radeon_irq_kms_fini(rdev);

		evergreen_pcie_gart_fini(rdev);

		rdev->accel_working = false;

	}

	if (rdev->accel_working) {

		r = radeon_ib_pool_init(rdev);

		if (r) {

			DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);

			rdev->accel_working = false;

		}

		r = r600_ib_test(rdev);

		if (r) {

			DRM_ERROR("radeon: failed testing IB (%d).\n", r);

			rdev->accel_working = false;

		}

	}

	return 0;

}
@@ -3285,11 +3346,12 @@ void evergreen_fini(struct radeon_device *rdev) 
	r700_cp_fini(rdev);

	r600_irq_fini(rdev);

	radeon_wb_fini(rdev);

	radeon_ib_pool_fini(rdev);

	r100_ib_fini(rdev);

	radeon_irq_kms_fini(rdev);

	evergreen_pcie_gart_fini(rdev);

	r600_vram_scratch_fini(rdev);

	radeon_gem_fini(rdev);

	radeon_semaphore_driver_fini(rdev);

	radeon_fence_driver_fini(rdev);

	radeon_agp_fini(rdev);

	radeon_bo_fini(rdev);

drivers/gpu/drm/radeon/evergreen_blit_kms.c

+125 −117

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/ni.c

+147 −90

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/radeon/nid.h

+33 −0
Original line number Diff line number Diff line
@@ -42,6 +42,9 @@ 
#define CAYMAN_MAX_TCC_MASK          0xFF



#define DMIF_ADDR_CONFIG  				0xBD4

#define	SRBM_GFX_CNTL				        0x0E44

#define		RINGID(x)					(((x) & 0x3) << 0)

#define		VMID(x)						(((x) & 0x7) << 0)

#define	SRBM_STATUS				        0x0E50



#define VM_CONTEXT0_REQUEST_RESPONSE			0x1470
@@ -394,6 +397,12 @@ 
#define	CP_RB0_RPTR_ADDR				0xC10C

#define	CP_RB0_RPTR_ADDR_HI				0xC110

#define	CP_RB0_WPTR					0xC114



#define CP_INT_CNTL                                     0xC124

#       define CNTX_BUSY_INT_ENABLE                     (1 << 19)

#       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)

#       define TIME_STAMP_INT_ENABLE                    (1 << 26)



#define	CP_RB1_BASE					0xC180

#define	CP_RB1_CNTL					0xC184

#define	CP_RB1_RPTR_ADDR				0xC188
@@ -411,6 +420,10 @@ 
#define	CP_ME_RAM_DATA					0xC160

#define	CP_DEBUG					0xC1FC



#define VGT_EVENT_INITIATOR                             0x28a90

#       define CACHE_FLUSH_AND_INV_EVENT_TS                     (0x14 << 0)

#       define CACHE_FLUSH_AND_INV_EVENT                        (0x16 << 0)



/*

 * PM4

 */
@@ -494,7 +507,27 @@ 
#define		PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)

#define	PACKET3_COND_WRITE				0x45

#define	PACKET3_EVENT_WRITE				0x46

#define		EVENT_TYPE(x)                           ((x) << 0)

#define		EVENT_INDEX(x)                          ((x) << 8)

                /* 0 - any non-TS event

		 * 1 - ZPASS_DONE

		 * 2 - SAMPLE_PIPELINESTAT

		 * 3 - SAMPLE_STREAMOUTSTAT*

		 * 4 - *S_PARTIAL_FLUSH

		 * 5 - TS events

		 */

#define	PACKET3_EVENT_WRITE_EOP				0x47

#define		DATA_SEL(x)                             ((x) << 29)

                /* 0 - discard

		 * 1 - send low 32bit data

		 * 2 - send 64bit data

		 * 3 - send 64bit counter value

		 */

#define		INT_SEL(x)                              ((x) << 24)

                /* 0 - none

		 * 1 - interrupt only (DATA_SEL = 0)

		 * 2 - interrupt when data write is confirmed

		 */

#define	PACKET3_EVENT_WRITE_EOS				0x48

#define	PACKET3_PREAMBLE_CNTL				0x4A

#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)