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Commit 4ba063ce authored by Gidon Studinski's avatar Gidon Studinski Committed by Gerrit - the friendly Code Review server
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msm: ipa3: add support for 64 bit immediate commands 



IPA 3.0 adds 64 bit support in HW. Change immediate commands structures
accordingly. This change does not take care of filtering and routing blocks
immediate commands which will be taken care of separately.

Change-Id: Ib39ab0e6f90e64d7e2364148bebb9b03dcda4ad5
Acked-by: default avatarAdy Abraham <adya@qti.qualcomm.com>
Signed-off-by: default avatarNadine Toledano <nadinet@codeaurora.org>
Signed-off-by: default avatarAmir Levy <alevy@codeaurora.org>
Signed-off-by: default avatarGidon Studinski <gidons@codeaurora.org>
parent 918d7829

drivers/platform/msm/ipa/ipa_dp.c

+0 −2
Original line number Diff line number Diff line
@@ -1384,8 +1384,6 @@ int ipa_tx_dp(enum ipa_client_type dst, struct sk_buff *skb, 
		}



		cmd->destination_pipe_index = dst_ep_idx;

		if (meta && meta->mbim_stream_id_valid)

			cmd->metadata = meta->mbim_stream_id;

		desc[0].opcode = IPA_IP_PACKET_INIT;

		desc[0].pyld = cmd;

		desc[0].len = sizeof(struct ipa_ip_packet_init);

drivers/platform/msm/ipa/ipa_v3/ipa.c

+19 −0
Original line number Diff line number Diff line
@@ -1177,6 +1177,8 @@ static int ipa_init_smem_region(int memory_region_size, 
	}



	memset(mem.base, 0, mem.size);

	cmd.skip_pipeline_clear = 0;

	cmd.pipeline_clear_options = IPA_HPS_CLEAR;

	cmd.size = mem.size;

	cmd.system_addr = mem.phys_base;

	cmd.local_addr = ipa_ctx->smem_restricted_bytes +
@@ -1398,6 +1400,9 @@ static int ipa_q6_clean_q6_tables(void) 
			 * Need to point v4 and v6 fltr tables to an empty

			 * table

			 */

			cmd[num_cmds].skip_pipeline_clear = 0;

			cmd[num_cmds].pipeline_clear_options =

				IPA_FULL_PIPELINE_CLEAR;

			cmd[num_cmds].size = mem.size;

			cmd[num_cmds].system_addr = mem.phys_base;

			cmd[num_cmds].local_addr =
@@ -1410,6 +1415,9 @@ static int ipa_q6_clean_q6_tables(void) 
			desc[num_cmds].type = IPA_IMM_CMD_DESC;

			num_cmds++;



			cmd[num_cmds].skip_pipeline_clear = 0;

			cmd[num_cmds].pipeline_clear_options =

				IPA_FULL_PIPELINE_CLEAR;

			cmd[num_cmds].size = mem.size;

			cmd[num_cmds].system_addr =  mem.phys_base;

			cmd[num_cmds].local_addr =
@@ -1428,6 +1436,9 @@ static int ipa_q6_clean_q6_tables(void) 
	for (index = IPA_MEM_PART(v4_modem_rt_index_lo);

		 index <= IPA_MEM_PART(v4_modem_rt_index_hi);

		 index++) {

		cmd[num_cmds].skip_pipeline_clear = 0;

		cmd[num_cmds].pipeline_clear_options =

			IPA_FULL_PIPELINE_CLEAR;

		cmd[num_cmds].size = mem.size;

		cmd[num_cmds].system_addr =  mem.phys_base;

		cmd[num_cmds].local_addr = ipa_ctx->smem_restricted_bytes +
@@ -1443,6 +1454,9 @@ static int ipa_q6_clean_q6_tables(void) 
	for (index = IPA_MEM_PART(v6_modem_rt_index_lo);

		 index <= IPA_MEM_PART(v6_modem_rt_index_hi);

		 index++) {

		cmd[num_cmds].skip_pipeline_clear = 0;

		cmd[num_cmds].pipeline_clear_options =

			IPA_FULL_PIPELINE_CLEAR;

		cmd[num_cmds].size = mem.size;

		cmd[num_cmds].system_addr =  mem.phys_base;

		cmd[num_cmds].local_addr = ipa_ctx->smem_restricted_bytes +
@@ -1476,6 +1490,7 @@ static void ipa_q6_disable_agg_reg(struct ipa_register_write *reg_write, 
				   int ep_idx)

{

	reg_write->skip_pipeline_clear = 0;

	reg_write->pipeline_clear_options = IPA_FULL_PIPELINE_CLEAR;



	reg_write->offset = IPA_ENDP_INIT_AGGR_N_OFST_v3_0(ep_idx);

	reg_write->value =
@@ -1526,6 +1541,8 @@ static int ipa_q6_set_ex_path_dis_agg(void) 
				BUG();

			}

			reg_write->skip_pipeline_clear = 0;

			reg_write->pipeline_clear_options =

				IPA_FULL_PIPELINE_CLEAR;

			reg_write->offset = IPA_ENDP_STATUS_n_OFST(ep_idx);

			reg_write->value =

				(ipa_get_ep_mapping(IPA_CLIENT_APPS_LAN_CONS) &
@@ -1750,6 +1767,8 @@ int _ipa_init_hdr_v3_0(void) 
	memset(mem.base, 0, mem.size);

	memset(&desc, 0, sizeof(desc));



	dma_cmd.skip_pipeline_clear = 0;

	dma_cmd.pipeline_clear_options = IPA_FULL_PIPELINE_CLEAR;

	dma_cmd.system_addr = mem.phys_base;

	dma_cmd.local_addr = ipa_ctx->smem_restricted_bytes +

		IPA_MEM_PART(modem_hdr_proc_ctx_ofst);

drivers/platform/msm/ipa/ipa_v3/ipa_dp.c

+0 −2
Original line number Diff line number Diff line
@@ -1353,8 +1353,6 @@ int ipa_tx_dp(enum ipa_client_type dst, struct sk_buff *skb, 
		}



		cmd->destination_pipe_index = dst_ep_idx;

		if (meta && meta->mbim_stream_id_valid)

			cmd->metadata = meta->mbim_stream_id;

		desc[0].opcode = IPA_IP_PACKET_INIT;

		desc[0].pyld = cmd;

		desc[0].len = sizeof(struct ipa_ip_packet_init);

drivers/platform/msm/ipa/ipa_v3/ipa_flt.c

+8 −0
Original line number Diff line number Diff line
@@ -724,6 +724,8 @@ int __ipa_commit_flt_v3(enum ipa_ip_type ip) 
		goto fail_send_cmd;

	}



	cmd[num_desc].skip_pipeline_clear = 0;

	cmd[num_desc].pipeline_clear_options = IPA_HPS_CLEAR;

	cmd[num_desc].size = 4;

	cmd[num_desc].system_addr = head1.phys_base;

	cmd[num_desc].local_addr = local_addrh;
@@ -757,6 +759,8 @@ int __ipa_commit_flt_v3(enum ipa_ip_type ip) 
				IPA_MEM_PART(v6_flt_ofst) +

				8 + i * 4;

		}

		cmd[num_desc].skip_pipeline_clear = 0;

		cmd[num_desc].pipeline_clear_options = IPA_HPS_CLEAR;

		cmd[num_desc].size = 4;

		cmd[num_desc].system_addr = head1.phys_base + 4 + i * 4;

		cmd[num_desc].local_addr = local_addrh;
@@ -787,6 +791,8 @@ int __ipa_commit_flt_v3(enum ipa_ip_type ip) 
				IPA_MEM_PART(v6_flt_ofst) +

				13 * 4 + (i - 11) * 4;

		}

		cmd[num_desc].skip_pipeline_clear = 0;

		cmd[num_desc].pipeline_clear_options = IPA_HPS_CLEAR;

		cmd[num_desc].size = 4;

		cmd[num_desc].system_addr = head2.phys_base + (i - 11) * 4;

		cmd[num_desc].local_addr = local_addrh;
@@ -799,6 +805,8 @@ int __ipa_commit_flt_v3(enum ipa_ip_type ip) 
	}



	if (lcl) {

		cmd[num_desc].skip_pipeline_clear = 0;

		cmd[num_desc].pipeline_clear_options = IPA_HPS_CLEAR;

		cmd[num_desc].size = body.size;

		cmd[num_desc].system_addr = body.phys_base;

		cmd[num_desc].local_addr = local_addrb;

drivers/platform/msm/ipa/ipa_v3/ipa_hdr.c

+6 −0
Original line number Diff line number Diff line
@@ -205,6 +205,8 @@ int __ipa_commit_hdr_v3_0(void) 
				IPA_MEM_PART(apps_hdr_size));

			goto end;

		} else {

			dma_cmd_hdr.skip_pipeline_clear = 0;

			dma_cmd_hdr.pipeline_clear_options = IPA_HPS_CLEAR;

			dma_cmd_hdr.system_addr = hdr_mem.phys_base;

			dma_cmd_hdr.size = hdr_mem.size;

			dma_cmd_hdr.local_addr =
@@ -239,6 +241,8 @@ int __ipa_commit_hdr_v3_0(void) 
				proc_ctx_size);

			goto end;

		} else {

			dma_cmd_ctx.skip_pipeline_clear = 0;

			dma_cmd_ctx.pipeline_clear_options = IPA_HPS_CLEAR;

			dma_cmd_ctx.system_addr = aligned_ctx_mem.phys_base;

			dma_cmd_ctx.size = aligned_ctx_mem.size;

			dma_cmd_ctx.local_addr =
@@ -257,6 +261,8 @@ int __ipa_commit_hdr_v3_0(void) 
				proc_ctx_size_ddr);

			goto end;

		} else {

			reg_write_cmd.skip_pipeline_clear = 0;

			reg_write_cmd.pipeline_clear_options = IPA_HPS_CLEAR;

			reg_write_cmd.offset = IPA_SYS_PKT_PROC_CNTXT_BASE_OFST;

			reg_write_cmd.value = aligned_ctx_mem.phys_base;

			reg_write_cmd.value_mask =