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Commit 4b60e5cb authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Clear scanline waits after disabling the pipe. 

If we disable the pipe and the GPU is currently waiting on a scanline
WAIT_FOR_EVENT, the GPU will hang. Fortunately, there is a magic bit
which we can write on i915+ to break this wait after disabling the
pipe.

References:

  Bug 29252 - [Arrandale] Hung WAIT_FOR_EVENT when running rss-glx-skyrocket
  https://bugs.freedesktop.org/show_bug.cgi?id=29252

  Bug 28964 - [i965gm] GPU infinite MI_WAIT_FOR_EVENT while watching video in Totem
  https://bugs.freedesktop.org/show_bug.cgi?id=28964



and many others.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
parent 37811fcc

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -295,6 +295,8 @@ 
#define   RING_VALID_MASK	0x00000001

#define   RING_VALID_MASK	0x00000001

#define   RING_VALID		0x00000001

#define   RING_VALID		0x00000001

#define   RING_INVALID		0x00000000

#define   RING_INVALID		0x00000000

#define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */

#define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */

#define PRB1_TAIL	0x02040 /* 915+ only */

#define PRB1_TAIL	0x02040 /* 915+ only */

#define PRB1_HEAD	0x02044 /* 915+ only */

#define PRB1_HEAD	0x02044 /* 915+ only */

#define PRB1_START	0x02048 /* 915+ only */

#define PRB1_START	0x02048 /* 915+ only */

drivers/gpu/drm/i915/intel_display.c

+29 −2
Original line number Original line Diff line number Diff line
@@ -2344,6 +2344,26 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) 
	}

	}

}

}





/*

 * When we disable a pipe, we need to clear any pending scanline wait events

 * to avoid hanging the ring, which we assume we are waiting on.

 */

static void intel_clear_scanline_wait(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 tmp;



	if (IS_GEN2(dev))

		/* Can't break the hang on i8xx */

		return;



	tmp = I915_READ(PRB0_CTL);

	if (tmp & RING_WAIT) {

		I915_WRITE(PRB0_CTL, tmp);

		POSTING_READ(PRB0_CTL);

	}

}



/**

/**

 * Sets the power management mode of the pipe and plane.

 * Sets the power management mode of the pipe and plane.

 */

 */
@@ -2366,7 +2386,8 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) 
	 * with multiple pipes prior to enabling to new pipe.

	 * with multiple pipes prior to enabling to new pipe.

	 *

	 *

	 * When switching off the display, make sure the cursor is

	 * When switching off the display, make sure the cursor is

	 * properly hidden prior to disabling the pipe.

	 * properly hidden and there are no pending waits prior to

	 * disabling the pipe.

	 */

	 */

	if (mode == DRM_MODE_DPMS_ON)

	if (mode == DRM_MODE_DPMS_ON)

		intel_update_watermarks(dev);

		intel_update_watermarks(dev);
@@ -2377,8 +2398,14 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) 




	if (mode == DRM_MODE_DPMS_ON)

	if (mode == DRM_MODE_DPMS_ON)

		intel_crtc_update_cursor(crtc);

		intel_crtc_update_cursor(crtc);

	else

	else {

		/* XXX Note that this is not a complete solution, but a hack

		 * to avoid the most frequently hit hang.

		 */

		intel_clear_scanline_wait(dev);



		intel_update_watermarks(dev);

		intel_update_watermarks(dev);

	}





	if (!dev->primary->master)

	if (!dev->primary->master)

		return;

		return;