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Commit 4a33bc03 authored by Vladislav Zolotarov's avatar Vladislav Zolotarov Committed by David S. Miller
Browse files

bnx2x: registers dump fixes 



Fixes in registers dump:
        - Properly calculate dump length for 57712.
        - Prevent HW blocks parity attentions when dumping registers in order to
prevent false parity errors handling.
        - Update the bnx2x_dump.h file: old one had a few bugs that could cause
fatal HW error as a result of a registers dump.

Signed-off-by: default avatarVladislav Zolotarov <vladz@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 0744db23

drivers/net/bnx2x/bnx2x.h

+1 −0
Original line number Diff line number Diff line
@@ -636,6 +636,7 @@ struct bnx2x_common { 


#define CHIP_METAL(bp)			(bp->common.chip_id & 0x00000ff0)

#define CHIP_BOND_ID(bp)		(bp->common.chip_id & 0x0000000f)

#define CHIP_PARITY_ENABLED(bp)	(CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))



	int			flash_size;

#define NVRAM_1MB_SIZE			0x20000	/* 1M bit in bytes */

drivers/net/bnx2x/bnx2x_dump.h

+569 −419

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/bnx2x/bnx2x_ethtool.c

+21 −1
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#include "bnx2x.h"

#include "bnx2x_cmn.h"

#include "bnx2x_dump.h"

#include "bnx2x_init.h"



/* Note: in the format strings below %s is replaced by the queue-name which is

 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
@@ -472,7 +473,7 @@ static int bnx2x_get_regs_len(struct net_device *dev) 
{

	struct bnx2x *bp = netdev_priv(dev);

	int regdump_len = 0;

	int i;

	int i, j, k;



	if (CHIP_IS_E1(bp)) {

		for (i = 0; i < REGS_COUNT; i++)
@@ -502,6 +503,15 @@ static int bnx2x_get_regs_len(struct net_device *dev) 
			if (IS_E2_ONLINE(wreg_addrs_e2[i].info))

				regdump_len += wreg_addrs_e2[i].size *

					(1 + wreg_addrs_e2[i].read_regs_count);



		for (i = 0; i < PAGE_MODE_VALUES_E2; i++)

			for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {

				for (k = 0; k < PAGE_READ_REGS_E2; k++)

					if (IS_E2_ONLINE(page_read_regs_e2[k].

							 info))

						regdump_len +=

						page_read_regs_e2[k].size;

			}

	}

	regdump_len *= 4;

	regdump_len += sizeof(struct dump_hdr);
@@ -539,6 +549,12 @@ static void bnx2x_get_regs(struct net_device *dev, 
	if (!netif_running(bp->dev))

		return;



	/* Disable parity attentions as long as following dump may

	 * cause false alarms by reading never written registers. We

	 * will re-enable parity attentions right after the dump.

	 */

	bnx2x_disable_blocks_parity(bp);



	dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;

	dump_hdr.dump_sign = dump_sign_all;

	dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
@@ -580,6 +596,10 @@ static void bnx2x_get_regs(struct net_device *dev, 


		bnx2x_read_pages_regs_e2(bp, p);

	}

	/* Re-enable parity attentions */

	bnx2x_clear_blocks_parity(bp);

	if (CHIP_PARITY_ENABLED(bp))

		bnx2x_enable_blocks_parity(bp);

}



#define PHY_FW_VER_LEN			20

drivers/net/bnx2x/bnx2x_init.h

+220 −0
Original line number Diff line number Diff line
@@ -192,5 +192,225 @@ struct src_ent { 
	u64 next;

};



/****************************************************************************

* Parity configuration

****************************************************************************/

#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2) \

{ \

	block##_REG_##block##_PRTY_MASK, \

	block##_REG_##block##_PRTY_STS_CLR, \

	en_mask, {m1, m1h, m2}, #block \

}



#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2) \

{ \

	block##_REG_##block##_PRTY_MASK_0, \

	block##_REG_##block##_PRTY_STS_CLR_0, \

	en_mask, {m1, m1h, m2}, #block"_0" \

}



#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2) \

{ \

	block##_REG_##block##_PRTY_MASK_1, \

	block##_REG_##block##_PRTY_STS_CLR_1, \

	en_mask, {m1, m1h, m2}, #block"_1" \

}



static const struct {

	u32 mask_addr;

	u32 sts_clr_addr;

	u32 en_mask;		/* Mask to enable parity attentions */

	struct {

		u32 e1;		/* 57710 */

		u32 e1h;	/* 57711 */

		u32 e2;		/* 57712 */

	} reg_mask;		/* Register mask (all valid bits) */

	char name[7];		/* Block's longest name is 6 characters long

				 * (name + suffix)

				 */

} bnx2x_blocks_parity_data[] = {

	/* bit 19 masked */

	/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */

	/* bit 5,18,20-31 */

	/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */

	/* bit 5 */

	/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20);	*/

	/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */

	/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */



	/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't

	 * want to handle "system kill" flow at the moment.

	 */

	BLOCK_PRTY_INFO(PXP, 0x3ffffff, 0x3ffffff, 0x3ffffff, 0x3ffffff),

	BLOCK_PRTY_INFO_0(PXP2,	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff),

	BLOCK_PRTY_INFO_1(PXP2,	0x7ff, 0x7f, 0x7f, 0x7ff),

	BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0),

	BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff),

	BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),

	BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff),

	BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),

	{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,

		GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0,

		{0xf, 0xf, 0xf}, "UPB"},

	{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,

		GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,

		{0xf, 0xf, 0xf}, "XPB"},

	BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),

	BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),

	BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf),

	BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),

	BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),

	BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),

	BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),

	BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),

	BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),

	BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),

	BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),

	BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),

	BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f),

	BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),

	BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f),

	BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),

	BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f),

	BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),

	BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f),

};





/* [28] MCP Latched rom_parity

 * [29] MCP Latched ump_rx_parity

 * [30] MCP Latched ump_tx_parity

 * [31] MCP Latched scpad_parity

 */

#define MISC_AEU_ENABLE_MCP_PRTY_BITS	\

	(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \

	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \

	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \

	 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)



/* Below registers control the MCP parity attention output. When

 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are

 * enabled, when cleared - disabled.

 */

static const u32 mcp_attn_ctl_regs[] = {

	MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,

	MISC_REG_AEU_ENABLE4_NIG_0,

	MISC_REG_AEU_ENABLE4_PXP_0,

	MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,

	MISC_REG_AEU_ENABLE4_NIG_1,

	MISC_REG_AEU_ENABLE4_PXP_1

};



static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)

{

	int i;

	u32 reg_val;



	for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {

		reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]);



		if (enable)

			reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;

		else

			reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;



		REG_WR(bp, mcp_attn_ctl_regs[i], reg_val);

	}

}



static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)

{

	if (CHIP_IS_E1(bp))

		return bnx2x_blocks_parity_data[idx].reg_mask.e1;

	else if (CHIP_IS_E1H(bp))

		return bnx2x_blocks_parity_data[idx].reg_mask.e1h;

	else

		return bnx2x_blocks_parity_data[idx].reg_mask.e2;

}



static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {

		u32 dis_mask = bnx2x_parity_reg_mask(bp, i);



		if (dis_mask) {

			REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,

			       dis_mask);

			DP(NETIF_MSG_HW, "Setting parity mask "

						 "for %s to\t\t0x%x\n",

				    bnx2x_blocks_parity_data[i].name, dis_mask);

		}

	}



	/* Disable MCP parity attentions */

	bnx2x_set_mcp_parity(bp, false);

}



/**

 * Clear the parity error status registers.

 */

static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)

{

	int i;

	u32 reg_val, mcp_aeu_bits =

		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |

		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |

		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |

		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;



	/* Clear SEM_FAST parities */

	REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);

	REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);

	REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);

	REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);



	for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {

		u32 reg_mask = bnx2x_parity_reg_mask(bp, i);



		if (reg_mask) {

			reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].

					 sts_clr_addr);

			if (reg_val & reg_mask)

				DP(NETIF_MSG_HW,

					    "Parity errors in %s: 0x%x\n",

					    bnx2x_blocks_parity_data[i].name,

					    reg_val & reg_mask);

		}

	}



	/* Check if there were parity attentions in MCP */

	reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);

	if (reg_val & mcp_aeu_bits)

		DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",

		   reg_val & mcp_aeu_bits);



	/* Clear parity attentions in MCP:

	 * [7]  clears Latched rom_parity

	 * [8]  clears Latched ump_rx_parity

	 * [9]  clears Latched ump_tx_parity

	 * [10] clears Latched scpad_parity (both ports)

	 */

	REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);

}



static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {

		u32 reg_mask = bnx2x_parity_reg_mask(bp, i);



		if (reg_mask)

			REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,

				bnx2x_blocks_parity_data[i].en_mask & reg_mask);

	}



	/* Enable MCP parity attentions */

	bnx2x_set_mcp_parity(bp, true);

}





#endif /* BNX2X_INIT_H */

drivers/net/bnx2x/bnx2x_main.c

+6 −51
Original line number Diff line number Diff line
@@ -3152,7 +3152,6 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) 
#define LOAD_COUNTER_MASK	(((u32)0x1 << LOAD_COUNTER_BITS) - 1)

#define RESET_DONE_FLAG_MASK	(~LOAD_COUNTER_MASK)

#define RESET_DONE_FLAG_SHIFT	LOAD_COUNTER_BITS

#define CHIP_PARITY_SUPPORTED(bp)   (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))



/*

 * should be run under rtnl lock
@@ -3527,7 +3526,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) 
	   try to handle this event */

	bnx2x_acquire_alr(bp);



	if (bnx2x_chk_parity_attn(bp)) {

	if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {

		bp->recovery_state = BNX2X_RECOVERY_INIT;

		bnx2x_set_reset_in_progress(bp);

		schedule_delayed_work(&bp->reset_task, 0);
@@ -4754,7 +4753,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp) 
	return 0; /* OK */

}



static void enable_blocks_attention(struct bnx2x *bp)

static void bnx2x_enable_blocks_attention(struct bnx2x *bp)

{

	REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);

	if (CHIP_IS_E2(bp))
@@ -4808,53 +4807,9 @@ static void enable_blocks_attention(struct bnx2x *bp) 
	REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);

	REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);

/*	REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */

	REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);		/* bit 3,4 masked */

	REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);		/* bit 3,4 masked */

}



static const struct {

	u32 addr;

	u32 mask;

} bnx2x_parity_mask[] = {

	{PXP_REG_PXP_PRTY_MASK,		0x3ffffff},

	{PXP2_REG_PXP2_PRTY_MASK_0,	0xffffffff},

	{PXP2_REG_PXP2_PRTY_MASK_1,	0x7f},

	{HC_REG_HC_PRTY_MASK,		0x7},

	{MISC_REG_MISC_PRTY_MASK,	0x1},

	{QM_REG_QM_PRTY_MASK,		0x0},

	{DORQ_REG_DORQ_PRTY_MASK,	0x0},

	{GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 0x0},

	{GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 0x0},

	{SRC_REG_SRC_PRTY_MASK,		0x4}, /* bit 2 */

	{CDU_REG_CDU_PRTY_MASK,		0x0},

	{CFC_REG_CFC_PRTY_MASK,		0x0},

	{DBG_REG_DBG_PRTY_MASK,		0x0},

	{DMAE_REG_DMAE_PRTY_MASK,	0x0},

	{BRB1_REG_BRB1_PRTY_MASK,	0x0},

	{PRS_REG_PRS_PRTY_MASK,		(1<<6)},/* bit 6 */

	{TSDM_REG_TSDM_PRTY_MASK,	0x18},	/* bit 3,4 */

	{CSDM_REG_CSDM_PRTY_MASK,	0x8},	/* bit 3 */

	{USDM_REG_USDM_PRTY_MASK,	0x38},  /* bit 3,4,5 */

	{XSDM_REG_XSDM_PRTY_MASK,	0x8},	/* bit 3 */

	{TSEM_REG_TSEM_PRTY_MASK_0,	0x0},

	{TSEM_REG_TSEM_PRTY_MASK_1,	0x0},

	{USEM_REG_USEM_PRTY_MASK_0,	0x0},

	{USEM_REG_USEM_PRTY_MASK_1,	0x0},

	{CSEM_REG_CSEM_PRTY_MASK_0,	0x0},

	{CSEM_REG_CSEM_PRTY_MASK_1,	0x0},

	{XSEM_REG_XSEM_PRTY_MASK_0,	0x0},

	{XSEM_REG_XSEM_PRTY_MASK_1,	0x0}

};



static void enable_blocks_parity(struct bnx2x *bp)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(bnx2x_parity_mask); i++)

		REG_WR(bp, bnx2x_parity_mask[i].addr,

			bnx2x_parity_mask[i].mask);

}





static void bnx2x_reset_common(struct bnx2x *bp)

{

	/* reset_common */
@@ -5350,9 +5305,9 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code) 
	/* clear PXP2 attentions */

	REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);



	enable_blocks_attention(bp);

	if (CHIP_PARITY_SUPPORTED(bp))

		enable_blocks_parity(bp);

	bnx2x_enable_blocks_attention(bp);

	if (CHIP_PARITY_ENABLED(bp))

		bnx2x_enable_blocks_parity(bp);



	if (!BP_NOMCP(bp)) {

		/* In E2 2-PORT mode, same ext phy is used for the two paths */