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Commit 48e7a5f1 authored by Daniel Vetter's avatar Daniel Vetter Committed by Dave Airlie
Browse files

drm/radeon: move asic structs to radeon_asic.c 



With these static structs gone, radeon_asic.h is a real header file
and can be used as such.

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 0a10c851

drivers/gpu/drm/radeon/radeon_asic.c

+487 −0
Original line number Diff line number Diff line
@@ -128,6 +128,493 @@ void radeon_agp_disable(struct radeon_device *rdev) 
/*

 * ASIC

 */

static struct radeon_asic r100_asic = {

	.init = &r100_init,

	.fini = &r100_fini,

	.suspend = &r100_suspend,

	.resume = &r100_resume,

	.vga_set_state = &r100_vga_set_state,

	.gpu_reset = &r100_gpu_reset,

	.gart_tlb_flush = &r100_pci_gart_tlb_flush,

	.gart_set_page = &r100_pci_gart_set_page,

	.cp_commit = &r100_cp_commit,

	.ring_start = &r100_ring_start,

	.ring_test = &r100_ring_test,

	.ring_ib_execute = &r100_ring_ib_execute,

	.irq_set = &r100_irq_set,

	.irq_process = &r100_irq_process,

	.get_vblank_counter = &r100_get_vblank_counter,

	.fence_ring_emit = &r100_fence_ring_emit,

	.cs_parse = &r100_cs_parse,

	.copy_blit = &r100_copy_blit,

	.copy_dma = NULL,

	.copy = &r100_copy_blit,

	.get_engine_clock = &radeon_legacy_get_engine_clock,

	.set_engine_clock = &radeon_legacy_set_engine_clock,

	.get_memory_clock = &radeon_legacy_get_memory_clock,

	.set_memory_clock = NULL,

	.get_pcie_lanes = NULL,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_legacy_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &r100_bandwidth_update,

	.hpd_init = &r100_hpd_init,

	.hpd_fini = &r100_hpd_fini,

	.hpd_sense = &r100_hpd_sense,

	.hpd_set_polarity = &r100_hpd_set_polarity,

	.ioctl_wait_idle = NULL,

};



static struct radeon_asic r200_asic = {

	.init = &r100_init,

	.fini = &r100_fini,

	.suspend = &r100_suspend,

	.resume = &r100_resume,

	.vga_set_state = &r100_vga_set_state,

	.gpu_reset = &r100_gpu_reset,

	.gart_tlb_flush = &r100_pci_gart_tlb_flush,

	.gart_set_page = &r100_pci_gart_set_page,

	.cp_commit = &r100_cp_commit,

	.ring_start = &r100_ring_start,

	.ring_test = &r100_ring_test,

	.ring_ib_execute = &r100_ring_ib_execute,

	.irq_set = &r100_irq_set,

	.irq_process = &r100_irq_process,

	.get_vblank_counter = &r100_get_vblank_counter,

	.fence_ring_emit = &r100_fence_ring_emit,

	.cs_parse = &r100_cs_parse,

	.copy_blit = &r100_copy_blit,

	.copy_dma = &r200_copy_dma,

	.copy = &r100_copy_blit,

	.get_engine_clock = &radeon_legacy_get_engine_clock,

	.set_engine_clock = &radeon_legacy_set_engine_clock,

	.get_memory_clock = &radeon_legacy_get_memory_clock,

	.set_memory_clock = NULL,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_legacy_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &r100_bandwidth_update,

	.hpd_init = &r100_hpd_init,

	.hpd_fini = &r100_hpd_fini,

	.hpd_sense = &r100_hpd_sense,

	.hpd_set_polarity = &r100_hpd_set_polarity,

	.ioctl_wait_idle = NULL,

};



static struct radeon_asic r300_asic = {

	.init = &r300_init,

	.fini = &r300_fini,

	.suspend = &r300_suspend,

	.resume = &r300_resume,

	.vga_set_state = &r100_vga_set_state,

	.gpu_reset = &r300_gpu_reset,

	.gart_tlb_flush = &r100_pci_gart_tlb_flush,

	.gart_set_page = &r100_pci_gart_set_page,

	.cp_commit = &r100_cp_commit,

	.ring_start = &r300_ring_start,

	.ring_test = &r100_ring_test,

	.ring_ib_execute = &r100_ring_ib_execute,

	.irq_set = &r100_irq_set,

	.irq_process = &r100_irq_process,

	.get_vblank_counter = &r100_get_vblank_counter,

	.fence_ring_emit = &r300_fence_ring_emit,

	.cs_parse = &r300_cs_parse,

	.copy_blit = &r100_copy_blit,

	.copy_dma = &r200_copy_dma,

	.copy = &r100_copy_blit,

	.get_engine_clock = &radeon_legacy_get_engine_clock,

	.set_engine_clock = &radeon_legacy_set_engine_clock,

	.get_memory_clock = &radeon_legacy_get_memory_clock,

	.set_memory_clock = NULL,

	.get_pcie_lanes = &rv370_get_pcie_lanes,

	.set_pcie_lanes = &rv370_set_pcie_lanes,

	.set_clock_gating = &radeon_legacy_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &r100_bandwidth_update,

	.hpd_init = &r100_hpd_init,

	.hpd_fini = &r100_hpd_fini,

	.hpd_sense = &r100_hpd_sense,

	.hpd_set_polarity = &r100_hpd_set_polarity,

	.ioctl_wait_idle = NULL,

};



static struct radeon_asic r300_asic_pcie = {

	.init = &r300_init,

	.fini = &r300_fini,

	.suspend = &r300_suspend,

	.resume = &r300_resume,

	.vga_set_state = &r100_vga_set_state,

	.gpu_reset = &r300_gpu_reset,

	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,

	.gart_set_page = &rv370_pcie_gart_set_page,

	.cp_commit = &r100_cp_commit,

	.ring_start = &r300_ring_start,

	.ring_test = &r100_ring_test,

	.ring_ib_execute = &r100_ring_ib_execute,

	.irq_set = &r100_irq_set,

	.irq_process = &r100_irq_process,

	.get_vblank_counter = &r100_get_vblank_counter,

	.fence_ring_emit = &r300_fence_ring_emit,

	.cs_parse = &r300_cs_parse,

	.copy_blit = &r100_copy_blit,

	.copy_dma = &r200_copy_dma,

	.copy = &r100_copy_blit,

	.get_engine_clock = &radeon_legacy_get_engine_clock,

	.set_engine_clock = &radeon_legacy_set_engine_clock,

	.get_memory_clock = &radeon_legacy_get_memory_clock,

	.set_memory_clock = NULL,

	.set_pcie_lanes = &rv370_set_pcie_lanes,

	.set_clock_gating = &radeon_legacy_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &r100_bandwidth_update,

	.hpd_init = &r100_hpd_init,

	.hpd_fini = &r100_hpd_fini,

	.hpd_sense = &r100_hpd_sense,

	.hpd_set_polarity = &r100_hpd_set_polarity,

	.ioctl_wait_idle = NULL,

};



static struct radeon_asic r420_asic = {

	.init = &r420_init,

	.fini = &r420_fini,

	.suspend = &r420_suspend,

	.resume = &r420_resume,

	.vga_set_state = &r100_vga_set_state,

	.gpu_reset = &r300_gpu_reset,

	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,

	.gart_set_page = &rv370_pcie_gart_set_page,

	.cp_commit = &r100_cp_commit,

	.ring_start = &r300_ring_start,

	.ring_test = &r100_ring_test,

	.ring_ib_execute = &r100_ring_ib_execute,

	.irq_set = &r100_irq_set,

	.irq_process = &r100_irq_process,

	.get_vblank_counter = &r100_get_vblank_counter,

	.fence_ring_emit = &r300_fence_ring_emit,

	.cs_parse = &r300_cs_parse,

	.copy_blit = &r100_copy_blit,

	.copy_dma = &r200_copy_dma,

	.copy = &r100_copy_blit,

	.get_engine_clock = &radeon_atom_get_engine_clock,

	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = &rv370_get_pcie_lanes,

	.set_pcie_lanes = &rv370_set_pcie_lanes,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &r100_bandwidth_update,

	.hpd_init = &r100_hpd_init,

	.hpd_fini = &r100_hpd_fini,

	.hpd_sense = &r100_hpd_sense,

	.hpd_set_polarity = &r100_hpd_set_polarity,

	.ioctl_wait_idle = NULL,

};



static struct radeon_asic rs400_asic = {

	.init = &rs400_init,

	.fini = &rs400_fini,

	.suspend = &rs400_suspend,

	.resume = &rs400_resume,

	.vga_set_state = &r100_vga_set_state,

	.gpu_reset = &r300_gpu_reset,

	.gart_tlb_flush = &rs400_gart_tlb_flush,

	.gart_set_page = &rs400_gart_set_page,

	.cp_commit = &r100_cp_commit,

	.ring_start = &r300_ring_start,

	.ring_test = &r100_ring_test,

	.ring_ib_execute = &r100_ring_ib_execute,

	.irq_set = &r100_irq_set,

	.irq_process = &r100_irq_process,

	.get_vblank_counter = &r100_get_vblank_counter,

	.fence_ring_emit = &r300_fence_ring_emit,

	.cs_parse = &r300_cs_parse,

	.copy_blit = &r100_copy_blit,

	.copy_dma = &r200_copy_dma,

	.copy = &r100_copy_blit,

	.get_engine_clock = &radeon_legacy_get_engine_clock,

	.set_engine_clock = &radeon_legacy_set_engine_clock,

	.get_memory_clock = &radeon_legacy_get_memory_clock,

	.set_memory_clock = NULL,

	.get_pcie_lanes = NULL,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_legacy_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &r100_bandwidth_update,

	.hpd_init = &r100_hpd_init,

	.hpd_fini = &r100_hpd_fini,

	.hpd_sense = &r100_hpd_sense,

	.hpd_set_polarity = &r100_hpd_set_polarity,

	.ioctl_wait_idle = NULL,

};



static struct radeon_asic rs600_asic = {

	.init = &rs600_init,

	.fini = &rs600_fini,

	.suspend = &rs600_suspend,

	.resume = &rs600_resume,

	.vga_set_state = &r100_vga_set_state,

	.gpu_reset = &r300_gpu_reset,

	.gart_tlb_flush = &rs600_gart_tlb_flush,

	.gart_set_page = &rs600_gart_set_page,

	.cp_commit = &r100_cp_commit,

	.ring_start = &r300_ring_start,

	.ring_test = &r100_ring_test,

	.ring_ib_execute = &r100_ring_ib_execute,

	.irq_set = &rs600_irq_set,

	.irq_process = &rs600_irq_process,

	.get_vblank_counter = &rs600_get_vblank_counter,

	.fence_ring_emit = &r300_fence_ring_emit,

	.cs_parse = &r300_cs_parse,

	.copy_blit = &r100_copy_blit,

	.copy_dma = &r200_copy_dma,

	.copy = &r100_copy_blit,

	.get_engine_clock = &radeon_atom_get_engine_clock,

	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = NULL,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &rs600_bandwidth_update,

	.hpd_init = &rs600_hpd_init,

	.hpd_fini = &rs600_hpd_fini,

	.hpd_sense = &rs600_hpd_sense,

	.hpd_set_polarity = &rs600_hpd_set_polarity,

	.ioctl_wait_idle = NULL,

};



static struct radeon_asic rs690_asic = {

	.init = &rs690_init,

	.fini = &rs690_fini,

	.suspend = &rs690_suspend,

	.resume = &rs690_resume,

	.vga_set_state = &r100_vga_set_state,

	.gpu_reset = &r300_gpu_reset,

	.gart_tlb_flush = &rs400_gart_tlb_flush,

	.gart_set_page = &rs400_gart_set_page,

	.cp_commit = &r100_cp_commit,

	.ring_start = &r300_ring_start,

	.ring_test = &r100_ring_test,

	.ring_ib_execute = &r100_ring_ib_execute,

	.irq_set = &rs600_irq_set,

	.irq_process = &rs600_irq_process,

	.get_vblank_counter = &rs600_get_vblank_counter,

	.fence_ring_emit = &r300_fence_ring_emit,

	.cs_parse = &r300_cs_parse,

	.copy_blit = &r100_copy_blit,

	.copy_dma = &r200_copy_dma,

	.copy = &r200_copy_dma,

	.get_engine_clock = &radeon_atom_get_engine_clock,

	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = NULL,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &rs690_bandwidth_update,

	.hpd_init = &rs600_hpd_init,

	.hpd_fini = &rs600_hpd_fini,

	.hpd_sense = &rs600_hpd_sense,

	.hpd_set_polarity = &rs600_hpd_set_polarity,

	.ioctl_wait_idle = NULL,

};



static struct radeon_asic rv515_asic = {

	.init = &rv515_init,

	.fini = &rv515_fini,

	.suspend = &rv515_suspend,

	.resume = &rv515_resume,

	.vga_set_state = &r100_vga_set_state,

	.gpu_reset = &rv515_gpu_reset,

	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,

	.gart_set_page = &rv370_pcie_gart_set_page,

	.cp_commit = &r100_cp_commit,

	.ring_start = &rv515_ring_start,

	.ring_test = &r100_ring_test,

	.ring_ib_execute = &r100_ring_ib_execute,

	.irq_set = &rs600_irq_set,

	.irq_process = &rs600_irq_process,

	.get_vblank_counter = &rs600_get_vblank_counter,

	.fence_ring_emit = &r300_fence_ring_emit,

	.cs_parse = &r300_cs_parse,

	.copy_blit = &r100_copy_blit,

	.copy_dma = &r200_copy_dma,

	.copy = &r100_copy_blit,

	.get_engine_clock = &radeon_atom_get_engine_clock,

	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = &rv370_get_pcie_lanes,

	.set_pcie_lanes = &rv370_set_pcie_lanes,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &rv515_bandwidth_update,

	.hpd_init = &rs600_hpd_init,

	.hpd_fini = &rs600_hpd_fini,

	.hpd_sense = &rs600_hpd_sense,

	.hpd_set_polarity = &rs600_hpd_set_polarity,

	.ioctl_wait_idle = NULL,

};



static struct radeon_asic r520_asic = {

	.init = &r520_init,

	.fini = &rv515_fini,

	.suspend = &rv515_suspend,

	.resume = &r520_resume,

	.vga_set_state = &r100_vga_set_state,

	.gpu_reset = &rv515_gpu_reset,

	.gart_tlb_flush = &rv370_pcie_gart_tlb_flush,

	.gart_set_page = &rv370_pcie_gart_set_page,

	.cp_commit = &r100_cp_commit,

	.ring_start = &rv515_ring_start,

	.ring_test = &r100_ring_test,

	.ring_ib_execute = &r100_ring_ib_execute,

	.irq_set = &rs600_irq_set,

	.irq_process = &rs600_irq_process,

	.get_vblank_counter = &rs600_get_vblank_counter,

	.fence_ring_emit = &r300_fence_ring_emit,

	.cs_parse = &r300_cs_parse,

	.copy_blit = &r100_copy_blit,

	.copy_dma = &r200_copy_dma,

	.copy = &r100_copy_blit,

	.get_engine_clock = &radeon_atom_get_engine_clock,

	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = &rv370_get_pcie_lanes,

	.set_pcie_lanes = &rv370_set_pcie_lanes,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r100_set_surface_reg,

	.clear_surface_reg = r100_clear_surface_reg,

	.bandwidth_update = &rv515_bandwidth_update,

	.hpd_init = &rs600_hpd_init,

	.hpd_fini = &rs600_hpd_fini,

	.hpd_sense = &rs600_hpd_sense,

	.hpd_set_polarity = &rs600_hpd_set_polarity,

	.ioctl_wait_idle = NULL,

};



static struct radeon_asic r600_asic = {

	.init = &r600_init,

	.fini = &r600_fini,

	.suspend = &r600_suspend,

	.resume = &r600_resume,

	.cp_commit = &r600_cp_commit,

	.vga_set_state = &r600_vga_set_state,

	.gpu_reset = &r600_gpu_reset,

	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,

	.gart_set_page = &rs600_gart_set_page,

	.ring_test = &r600_ring_test,

	.ring_ib_execute = &r600_ring_ib_execute,

	.irq_set = &r600_irq_set,

	.irq_process = &r600_irq_process,

	.get_vblank_counter = &rs600_get_vblank_counter,

	.fence_ring_emit = &r600_fence_ring_emit,

	.cs_parse = &r600_cs_parse,

	.copy_blit = &r600_copy_blit,

	.copy_dma = &r600_copy_blit,

	.copy = &r600_copy_blit,

	.get_engine_clock = &radeon_atom_get_engine_clock,

	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = &rv370_get_pcie_lanes,

	.set_pcie_lanes = NULL,

	.set_clock_gating = NULL,

	.set_surface_reg = r600_set_surface_reg,

	.clear_surface_reg = r600_clear_surface_reg,

	.bandwidth_update = &rv515_bandwidth_update,

	.hpd_init = &r600_hpd_init,

	.hpd_fini = &r600_hpd_fini,

	.hpd_sense = &r600_hpd_sense,

	.hpd_set_polarity = &r600_hpd_set_polarity,

	.ioctl_wait_idle = r600_ioctl_wait_idle,

};



static struct radeon_asic rv770_asic = {

	.init = &rv770_init,

	.fini = &rv770_fini,

	.suspend = &rv770_suspend,

	.resume = &rv770_resume,

	.cp_commit = &r600_cp_commit,

	.gpu_reset = &rv770_gpu_reset,

	.vga_set_state = &r600_vga_set_state,

	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,

	.gart_set_page = &rs600_gart_set_page,

	.ring_test = &r600_ring_test,

	.ring_ib_execute = &r600_ring_ib_execute,

	.irq_set = &r600_irq_set,

	.irq_process = &r600_irq_process,

	.get_vblank_counter = &rs600_get_vblank_counter,

	.fence_ring_emit = &r600_fence_ring_emit,

	.cs_parse = &r600_cs_parse,

	.copy_blit = &r600_copy_blit,

	.copy_dma = &r600_copy_blit,

	.copy = &r600_copy_blit,

	.get_engine_clock = &radeon_atom_get_engine_clock,

	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.get_pcie_lanes = &rv370_get_pcie_lanes,

	.set_pcie_lanes = NULL,

	.set_clock_gating = &radeon_atom_set_clock_gating,

	.set_surface_reg = r600_set_surface_reg,

	.clear_surface_reg = r600_clear_surface_reg,

	.bandwidth_update = &rv515_bandwidth_update,

	.hpd_init = &r600_hpd_init,

	.hpd_fini = &r600_hpd_fini,

	.hpd_sense = &r600_hpd_sense,

	.hpd_set_polarity = &r600_hpd_set_polarity,

	.ioctl_wait_idle = r600_ioctl_wait_idle,

};



static struct radeon_asic evergreen_asic = {

	.init = &evergreen_init,

	.fini = &evergreen_fini,

	.suspend = &evergreen_suspend,

	.resume = &evergreen_resume,

	.cp_commit = NULL,

	.gpu_reset = &evergreen_gpu_reset,

	.vga_set_state = &r600_vga_set_state,

	.gart_tlb_flush = &r600_pcie_gart_tlb_flush,

	.gart_set_page = &rs600_gart_set_page,

	.ring_test = NULL,

	.ring_ib_execute = NULL,

	.irq_set = NULL,

	.irq_process = NULL,

	.get_vblank_counter = NULL,

	.fence_ring_emit = NULL,

	.cs_parse = NULL,

	.copy_blit = NULL,

	.copy_dma = NULL,

	.copy = NULL,

	.get_engine_clock = &radeon_atom_get_engine_clock,

	.set_engine_clock = &radeon_atom_set_engine_clock,

	.get_memory_clock = &radeon_atom_get_memory_clock,

	.set_memory_clock = &radeon_atom_set_memory_clock,

	.set_pcie_lanes = NULL,

	.set_clock_gating = NULL,

	.set_surface_reg = r600_set_surface_reg,

	.clear_surface_reg = r600_clear_surface_reg,

	.bandwidth_update = &evergreen_bandwidth_update,

	.hpd_init = &evergreen_hpd_init,

	.hpd_fini = &evergreen_hpd_fini,

	.hpd_sense = &evergreen_hpd_sense,

	.hpd_set_polarity = &evergreen_hpd_set_polarity,

};



int radeon_asic_init(struct radeon_device *rdev)

{

	radeon_register_accessor_init(rdev);

drivers/gpu/drm/radeon/radeon_asic.h

+0 −489

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