Merge branch 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc (48924449) · Commits · e / devices / android_kernel_xiaomi_markw

arch/powerpc/kernel/cputable.c

+0 −12

Original line number	Original line	Diff line number	Diff line
	@@ -722,18 +722,6 @@ struct cpu_spec cpu_specs[] = {
	.oprofile_type = PPC_OPROFILE_G4,		.oprofile_type = PPC_OPROFILE_G4,
	.platform = "ppc7450",		.platform = "ppc7450",
	},		},
	{ /* 8641 */
	.pvr_mask = 0xffffffff,
	.pvr_value = 0x80040010,
	.cpu_name = "8641",
	.cpu_features = CPU_FTRS_7447A,
	.cpu_user_features = COMMON_USER \| PPC_FEATURE_HAS_ALTIVEC_COMP,
	.icache_bsize = 32,
	.dcache_bsize = 32,
	.num_pmcs = 6,
	.cpu_setup = __setup_cpu_745x
	},

	{ /* 82xx (8240, 8245, 8260 are all 603e cores) */		{ /* 82xx (8240, 8245, 8260 are all 603e cores) */
	.pvr_mask = 0x7fff0000,		.pvr_mask = 0x7fff0000,
	.pvr_value = 0x00810000,		.pvr_value = 0x00810000,

arch/powerpc/platforms/86xx/mpc86xx.h

+5 −3

Original line number	Original line	Diff line number	Diff line
	@@ -15,11 +15,13 @@
	* mpc86xx_* files. Mostly for use by mpc86xx_setup().		* mpc86xx_* files. Mostly for use by mpc86xx_setup().
	*/		*/

	extern int __init add_bridge(struct device_node *dev);		extern int add_bridge(struct device_node *dev);

	extern void __init setup_indirect_pcie(struct pci_controller *hose,		extern int mpc86xx_exclude_device(u_char bus, u_char devfn);

			extern void setup_indirect_pcie(struct pci_controller *hose,
	u32 cfg_addr, u32 cfg_data);		u32 cfg_addr, u32 cfg_data);
	extern void __init setup_indirect_pcie_nomap(struct pci_controller *hose,		extern void setup_indirect_pcie_nomap(struct pci_controller *hose,
	void __iomem *cfg_addr,		void __iomem *cfg_addr,
	void __iomem *cfg_data);		void __iomem *cfg_data);

arch/powerpc/platforms/86xx/mpc86xx_hpcn.c

+121 −7

Original line number	Original line	Diff line number	Diff line
	@@ -35,6 +35,7 @@
	#include <sysdev/fsl_soc.h>		#include <sysdev/fsl_soc.h>

	#include "mpc86xx.h"		#include "mpc86xx.h"
			#include "mpc8641_hpcn.h"

	#ifndef CONFIG_PCI		#ifndef CONFIG_PCI
	unsigned long isa_io_base = 0;		unsigned long isa_io_base = 0;
	@@ -185,17 +186,130 @@ mpc86xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
	return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;		return PCI_IRQ_TABLE_LOOKUP + I8259_OFFSET;
	}		}

			static void __devinit quirk_ali1575(struct pci_dev *dev)
			{
			unsigned short temp;

	int		/*
	mpc86xx_exclude_device(u_char bus, u_char devfn)		* ALI1575 interrupts route table setup:
			*
			* IRQ pin IRQ#
			* PIRQA ---- 3
			* PIRQB ---- 4
			* PIRQC ---- 5
			* PIRQD ---- 6
			* PIRQE ---- 9
			* PIRQF ---- 10
			* PIRQG ---- 11
			* PIRQH ---- 12
			*
			* interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
			* PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
			*/
			pci_write_config_dword(dev, 0x48, 0xb9317542);

			/* USB 1.1 OHCI controller 1, interrupt: PIRQE */
			pci_write_config_byte(dev, 0x86, 0x0c);

			/* USB 1.1 OHCI controller 2, interrupt: PIRQF */
			pci_write_config_byte(dev, 0x87, 0x0d);

			/* USB 1.1 OHCI controller 3, interrupt: PIRQH */
			pci_write_config_byte(dev, 0x88, 0x0f);

			/* USB 2.0 controller, interrupt: PIRQ7 */
			pci_write_config_byte(dev, 0x74, 0x06);

			/* Audio controller, interrupt: PIRQE */
			pci_write_config_byte(dev, 0x8a, 0x0c);

			/* Modem controller, interrupt: PIRQF */
			pci_write_config_byte(dev, 0x8b, 0x0d);

			/* HD audio controller, interrupt: PIRQG */
			pci_write_config_byte(dev, 0x8c, 0x0e);

			/* Serial ATA interrupt: PIRQD */
			pci_write_config_byte(dev, 0x8d, 0x0b);

			/* SMB interrupt: PIRQH */
			pci_write_config_byte(dev, 0x8e, 0x0f);

			/* PMU ACPI SCI interrupt: PIRQH */
			pci_write_config_byte(dev, 0x8f, 0x0f);

			/* Primary PATA IDE IRQ: 14
			* Secondary PATA IDE IRQ: 15
			*/
			pci_write_config_byte(dev, 0x44, 0x3d);
			pci_write_config_byte(dev, 0x75, 0x0f);

			/* Set IRQ14 and IRQ15 to legacy IRQs */
			pci_read_config_word(dev, 0x46, &temp);
			temp \|= 0xc000;
			pci_write_config_word(dev, 0x46, temp);

			/* Set i8259 interrupt trigger
			* IRQ 3: Level
			* IRQ 4: Level
			* IRQ 5: Level
			* IRQ 6: Level
			* IRQ 7: Level
			* IRQ 9: Level
			* IRQ 10: Level
			* IRQ 11: Level
			* IRQ 12: Level
			* IRQ 14: Edge
			* IRQ 15: Edge
			*/
			outb(0xfa, 0x4d0);
			outb(0x1e, 0x4d1);
			}

			static void __devinit quirk_uli5288(struct pci_dev *dev)
	{		{
	#if !defined(CONFIG_PCI)		unsigned char c;
	if (bus == 0 && PCI_SLOT(devfn) == 0)
	return PCIBIOS_DEVICE_NOT_FOUND;		pci_read_config_byte(dev,0x83,&c);
	#endif		c \|= 0x80;
			pci_write_config_byte(dev, 0x83, c);

			pci_write_config_byte(dev, 0x09, 0x01);
			pci_write_config_byte(dev, 0x0a, 0x06);

	return PCIBIOS_SUCCESSFUL;		pci_read_config_byte(dev,0x83,&c);
			c &= 0x7f;
			pci_write_config_byte(dev, 0x83, c);

			pci_read_config_byte(dev,0x84,&c);
			c \|= 0x01;
			pci_write_config_byte(dev, 0x84, c);
			}

			static void __devinit quirk_uli5229(struct pci_dev *dev)
			{
			unsigned short temp;
			pci_write_config_word(dev, 0x04, 0x0405);
			pci_read_config_word(dev, 0x4a, &temp);
			temp \|= 0x1000;
			pci_write_config_word(dev, 0x4a, temp);
	}		}

			static void __devinit early_uli5249(struct pci_dev *dev)
			{
			unsigned char temp;
			pci_write_config_word(dev, 0x04, 0x0007);
			pci_read_config_byte(dev, 0x7c, &temp);
			pci_write_config_byte(dev, 0x7c, 0x80);
			pci_write_config_byte(dev, 0x09, 0x01);
			pci_write_config_byte(dev, 0x7c, temp);
			dev->class \|= 0x1;
			}

			DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
			DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
			DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
			DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
	#endif /* CONFIG_PCI */		#endif /* CONFIG_PCI */

arch/powerpc/platforms/86xx/mpc86xx_smp.c

+4 −5

Original line number	Original line	Diff line number	Diff line
	@@ -33,8 +33,8 @@ extern unsigned long __secondary_hold_acknowledge;
	static void __init		static void __init
	smp_86xx_release_core(int nr)		smp_86xx_release_core(int nr)
	{		{
	void *mcm_vaddr;		__be32 __iomem *mcm_vaddr;
	unsigned long vaddr, pcr;		unsigned long pcr;

	if (nr < 0 \|\| nr >= NR_CPUS)		if (nr < 0 \|\| nr >= NR_CPUS)
	return;		return;
	@@ -44,10 +44,9 @@ smp_86xx_release_core(int nr)
	*/		*/
	mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET,		mcm_vaddr = ioremap(get_immrbase() + MPC86xx_MCM_OFFSET,
	MPC86xx_MCM_SIZE);		MPC86xx_MCM_SIZE);
	vaddr = (unsigned long)mcm_vaddr + MCM_PORT_CONFIG_OFFSET;		pcr = in_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2));
	pcr = in_be32((volatile unsigned *)vaddr);
	pcr \|= 1 << (nr + 24);		pcr \|= 1 << (nr + 24);
	out_be32((volatile unsigned *)vaddr, pcr);		out_be32(mcm_vaddr + (MCM_PORT_CONFIG_OFFSET >> 2), pcr);
	}		}

arch/powerpc/platforms/86xx/pci.c

+8 −128

Original line number	Original line	Diff line number	Diff line
	@@ -121,15 +121,12 @@ static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource
	static void __init		static void __init
	mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)		mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
	{		{
	volatile struct ccsr_pex *pcie;
	u16 cmd;		u16 cmd;
	unsigned int temps;		unsigned int temps;

	DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",		DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
	pcie_offset, pcie_size);		pcie_offset, pcie_size);

	pcie = ioremap(pcie_offset, pcie_size);

	early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);		early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
	cmd \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY		cmd \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY
	\| PCI_COMMAND_IO;		\| PCI_COMMAND_IO;
	@@ -143,6 +140,14 @@ mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
	early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps);		early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps);
	}		}

			int mpc86xx_exclude_device(u_char bus, u_char devfn)
			{
			if (bus == 0 && PCI_SLOT(devfn) == 0)
			return PCIBIOS_DEVICE_NOT_FOUND;

			return PCIBIOS_SUCCESSFUL;
			}

	int __init add_bridge(struct device_node *dev)		int __init add_bridge(struct device_node *dev)
	{		{
	int len;		int len;
	@@ -197,128 +202,3 @@ int __init add_bridge(struct device_node *dev)

	return 0;		return 0;
	}		}

	static void __devinit quirk_ali1575(struct pci_dev *dev)
	{
	unsigned short temp;

	/*
	* ALI1575 interrupts route table setup:
	*
	* IRQ pin IRQ#
	* PIRQA ---- 3
	* PIRQB ---- 4
	* PIRQC ---- 5
	* PIRQD ---- 6
	* PIRQE ---- 9
	* PIRQF ---- 10
	* PIRQG ---- 11
	* PIRQH ---- 12
	*
	* interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
	* PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
	*/
	pci_write_config_dword(dev, 0x48, 0xb9317542);

	/* USB 1.1 OHCI controller 1, interrupt: PIRQE */
	pci_write_config_byte(dev, 0x86, 0x0c);

	/* USB 1.1 OHCI controller 2, interrupt: PIRQF */
	pci_write_config_byte(dev, 0x87, 0x0d);

	/* USB 1.1 OHCI controller 3, interrupt: PIRQH */
	pci_write_config_byte(dev, 0x88, 0x0f);

	/* USB 2.0 controller, interrupt: PIRQ7 */
	pci_write_config_byte(dev, 0x74, 0x06);

	/* Audio controller, interrupt: PIRQE */
	pci_write_config_byte(dev, 0x8a, 0x0c);

	/* Modem controller, interrupt: PIRQF */
	pci_write_config_byte(dev, 0x8b, 0x0d);

	/* HD audio controller, interrupt: PIRQG */
	pci_write_config_byte(dev, 0x8c, 0x0e);

	/* Serial ATA interrupt: PIRQD */
	pci_write_config_byte(dev, 0x8d, 0x0b);

	/* SMB interrupt: PIRQH */
	pci_write_config_byte(dev, 0x8e, 0x0f);

	/* PMU ACPI SCI interrupt: PIRQH */
	pci_write_config_byte(dev, 0x8f, 0x0f);

	/* Primary PATA IDE IRQ: 14
	* Secondary PATA IDE IRQ: 15
	*/
	pci_write_config_byte(dev, 0x44, 0x3d);
	pci_write_config_byte(dev, 0x75, 0x0f);

	/* Set IRQ14 and IRQ15 to legacy IRQs */
	pci_read_config_word(dev, 0x46, &temp);
	temp \|= 0xc000;
	pci_write_config_word(dev, 0x46, temp);

	/* Set i8259 interrupt trigger
	* IRQ 3: Level
	* IRQ 4: Level
	* IRQ 5: Level
	* IRQ 6: Level
	* IRQ 7: Level
	* IRQ 9: Level
	* IRQ 10: Level
	* IRQ 11: Level
	* IRQ 12: Level
	* IRQ 14: Edge
	* IRQ 15: Edge
	*/
	outb(0xfa, 0x4d0);
	outb(0x1e, 0x4d1);
	}

	static void __devinit quirk_uli5288(struct pci_dev *dev)
	{
	unsigned char c;

	pci_read_config_byte(dev,0x83,&c);
	c \|= 0x80;
	pci_write_config_byte(dev, 0x83, c);

	pci_write_config_byte(dev, 0x09, 0x01);
	pci_write_config_byte(dev, 0x0a, 0x06);

	pci_read_config_byte(dev,0x83,&c);
	c &= 0x7f;
	pci_write_config_byte(dev, 0x83, c);

	pci_read_config_byte(dev,0x84,&c);
	c \|= 0x01;
	pci_write_config_byte(dev, 0x84, c);
	}

	static void __devinit quirk_uli5229(struct pci_dev *dev)
	{
	unsigned short temp;
	pci_write_config_word(dev, 0x04, 0x0405);
	pci_read_config_word(dev, 0x4a, &temp);
	temp \|= 0x1000;
	pci_write_config_word(dev, 0x4a, temp);
	}

	static void __devinit early_uli5249(struct pci_dev *dev)
	{
	unsigned char temp;
	pci_write_config_word(dev, 0x04, 0x0007);
	pci_read_config_byte(dev, 0x7c, &temp);
	pci_write_config_byte(dev, 0x7c, 0x80);
	pci_write_config_byte(dev, 0x09, 0x01);
	pci_write_config_byte(dev, 0x7c, temp);
	dev->class \|= 0x1;
	}

	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
	DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
	DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);