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Commit 47e9dedb authored by Sonic Zhang's avatar Sonic Zhang Committed by Mike Frysinger
Browse files

Blackfin: add blackfin_invalidate_entire_icache for SMP systems 



The KGDB code uses this when switching processors to make sure the icache
is in a valid state.

Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 2466ac65

arch/blackfin/include/asm/cache.h

+8 −3
Original line number Diff line number Diff line
@@ -34,9 +34,13 @@ 
#define L1_CACHE_SHIFT_MAX	5



#if defined(CONFIG_SMP) && \

    !defined(CONFIG_BFIN_CACHE_COHERENT) && \

    defined(CONFIG_BFIN_DCACHE)

    !defined(CONFIG_BFIN_CACHE_COHERENT)

# if defined(CONFIG_BFIN_ICACHE)

# define __ARCH_SYNC_CORE_ICACHE

# endif

# if defined(CONFIG_BFIN_DCACHE)

# define __ARCH_SYNC_CORE_DCACHE

# endif

#ifndef __ASSEMBLY__

asmlinkage void __raw_smp_mark_barrier_asm(void);

asmlinkage void __raw_smp_check_barrier_asm(void);
@@ -51,6 +55,7 @@ static inline void smp_check_barrier(void) 
}



void resync_core_dcache(void);

void resync_core_icache(void);

#endif

#endif

arch/blackfin/include/asm/cacheflush.h

+1 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned lo 
extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);

extern void blackfin_dflush_page(void *page);

extern void blackfin_invalidate_entire_dcache(void);

extern void blackfin_invalidate_entire_icache(void);



#define flush_dcache_mmap_lock(mapping)		do { } while (0)

#define flush_dcache_mmap_unlock(mapping)	do { } while (0)

arch/blackfin/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ struct blackfin_cpudata { 
	unsigned int dmemctl;

	unsigned long loops_per_jiffy;

	unsigned long dcache_invld_count;

	unsigned long icache_invld_count;

};



DECLARE_PER_CPU(struct blackfin_cpudata, cpu_data);

arch/blackfin/kernel/setup.c

+3 −0
Original line number Diff line number Diff line
@@ -1181,6 +1181,9 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
#ifdef __ARCH_SYNC_CORE_DCACHE

	seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", cpudata->dcache_invld_count);

#endif

#ifdef __ARCH_SYNC_CORE_ICACHE

	seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count);

#endif

#ifdef CONFIG_BFIN_ICACHE_LOCK

	switch ((cpudata->imemctl >> 3) & WAYALL_L) {

	case WAY0_L:

arch/blackfin/mach-common/cache-c.c

+13 −1
Original line number Diff line number Diff line
@@ -16,9 +16,21 @@ 
void blackfin_invalidate_entire_dcache(void)

{

	u32 dmem = bfin_read_DMEM_CONTROL();

	SSYNC();

	bfin_write_DMEM_CONTROL(dmem & ~0xc);

	SSYNC();

	bfin_write_DMEM_CONTROL(dmem);

	SSYNC();

}



/* Invalidate the Entire Instruction cache by

 * clearing IMC bit

 */

void blackfin_invalidate_entire_icache(void)

{

	u32 imem = bfin_read_IMEM_CONTROL();

	bfin_write_IMEM_CONTROL(imem & ~0x4);

	SSYNC();

	bfin_write_IMEM_CONTROL(imem);

	SSYNC();

}