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Commit 476b679a authored by Benoit Cousson's avatar Benoit Cousson
Browse files

arm/dts: OMAP3+: Add mpu, dsp and iva nodes 



Add nodes for devices used by PM code (mpu, dsp, iva).

Add a cpus node as well as recommended in the DT spec.

Remove mpu, dsp, iva devices init if is populated.

Signed-off-by: default avatarBenoit Cousson <b-cousson@ti.com>
Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
Cc: Kevin Hilman <khilman@ti.com>
parent ad8dfac6

Documentation/devicetree/bindings/arm/omap/dsp.txt

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* TI - DSP (Digital Signal Processor)



TI DSP included in OMAP SoC



Required properties:

- compatible : Should be "ti,omap3-c64" for OMAP3 & 4

- ti,hwmods: "dsp"



Examples:



dsp {

    compatible = "ti,omap3-c64";

    ti,hwmods = "dsp";

};

Documentation/devicetree/bindings/arm/omap/iva.txt

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* TI - IVA (Imaging and Video Accelerator) subsystem



The IVA contain various audio, video or imaging HW accelerator

depending of the version.



Required properties:

- compatible : Should be:

  - "ti,ivahd" for OMAP4

  - "ti,iva2.2" for OMAP3

  - "ti,iva2.1" for OMAP2430

  - "ti,iva1" for OMAP2420

- ti,hwmods: "iva"



Examples:



iva {

    compatible = "ti,ivahd", "ti,iva";

    ti,hwmods = "iva";

};

Documentation/devicetree/bindings/arm/omap/mpu.txt

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* TI - MPU (Main Processor Unit) subsystem



The MPU subsystem contain one or several ARM cores

depending of the version.

The MPU contain CPUs, GIC, L2 cache and a local PRCM.



Required properties:

- compatible : Should be "ti,omap3-mpu" for OMAP3

               Should be "ti,omap4-mpu" for OMAP4

- ti,hwmods: "mpu"



Examples:



- For an OMAP4 SMP system:



mpu {

    compatible = "ti,omap4-mpu";

    ti,hwmods = "mpu";

};





- For an OMAP3 monocore system:



mpu {

    compatible = "ti,omap3-mpu";

    ti,hwmods = "mpu";

};

arch/arm/boot/dts/omap3.dtsi

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@@ -13,12 +13,31 @@ 
/ {

	compatible = "ti,omap3430", "ti,omap3";



	cpus {

		cpu@0 {

			compatible = "arm,cortex-a8";

		};

	};



	/*

	 * The soc node represents the soc top level view. It is uses for IPs

	 * that are not memory mapped in the MPU view or for the MPU itself.

	 */

	soc {

		compatible = "ti,omap-infra";

		mpu {

			compatible = "ti,omap3-mpu";

			ti,hwmods = "mpu";

		};



		iva {

			compatible = "ti,iva2.2";

			ti,hwmods = "iva";



			dsp {

				compatible = "ti,omap3-c64";

			};

		};

	};



	/*

arch/arm/boot/dts/omap4.dtsi

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@@ -23,12 +23,35 @@ 
	aliases {

	};



	cpus {

		cpu@0 {

			compatible = "arm,cortex-a9";

		};

		cpu@1 {

			compatible = "arm,cortex-a9";

		};

	};



	/*

	 * The soc node represents the soc top level view. It is uses for IPs

	 * that are not memory mapped in the MPU view or for the MPU itself.

	 */

	soc {

		compatible = "ti,omap-infra";

		mpu {

			compatible = "ti,omap4-mpu";

			ti,hwmods = "mpu";

		};



		dsp {

			compatible = "ti,omap3-c64";

			ti,hwmods = "dsp";

		};



		iva {

			compatible = "ti,ivahd";

			ti,hwmods = "iva";

		};

	};



	/*