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Commit 473b8a2d authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Cleanup RBBM clock control defaults"

parents 60cb19e8 701112bb

drivers/gpu/msm/a3xx_reg.h

+1 −8
Original line number Diff line number Diff line
@@ -857,16 +857,9 @@ 
#define RBBM_BLOCK_ID_MARB_3           0x2b



/* RBBM_CLOCK_CTL default value */

#define A304_RBBM_CLOCK_CTL_DEFAULT   0xAAAAAAAA

#define A305_RBBM_CLOCK_CTL_DEFAULT   0xAAAAAAAA

#define A305C_RBBM_CLOCK_CTL_DEFAULT  0xAAAAAAAA

#define A306_RBBM_CLOCK_CTL_DEFAULT   0xAAAAAAAA

#define A306A_RBBM_CLOCK_CTL_DEFAULT  0xAAAAAAAA

#define A310_RBBM_CLOCK_CTL_DEFAULT   0xAAAAAAAA

#define A3XX_RBBM_CLOCK_CTL_DEFAULT   0xAAAAAAAA

#define A320_RBBM_CLOCK_CTL_DEFAULT   0xBFFFFFFF

#define A330_RBBM_CLOCK_CTL_DEFAULT   0xBFFCFFFF

#define A330v2_RBBM_CLOCK_CTL_DEFAULT 0xAAAAAAAA

#define A305B_RBBM_CLOCK_CTL_DEFAULT  0xAAAAAAAA



#define A330_RBBM_GPR0_CTL_DEFAULT    0x00000000

#define A330v2_RBBM_GPR0_CTL_DEFAULT  0x05515455

drivers/gpu/msm/adreno.h

+0 −3
Original line number Diff line number Diff line
@@ -813,9 +813,6 @@ void adreno_shadermem_regread(struct kgsl_device *device, 
						unsigned int offsetwords,

						unsigned int *value);



unsigned int adreno_a3xx_rbbm_clock_ctl_default(struct adreno_device

							*adreno_dev);



void adreno_snapshot(struct kgsl_device *device,

		struct kgsl_snapshot *snapshot,

		struct kgsl_context *context);

drivers/gpu/msm/adreno_a3xx.c

+4 −19
Original line number Diff line number Diff line
@@ -109,31 +109,16 @@ const unsigned int a3xx_cp_addr_regs[ADRENO_CP_ADDR_MAX] = { 
				A3XX_SP_FS_OBJ_START_REG),

};



unsigned int adreno_a3xx_rbbm_clock_ctl_default(struct adreno_device

static unsigned int adreno_a3xx_rbbm_clock_ctl_default(struct adreno_device

							*adreno_dev)

{

	if (adreno_is_a304(adreno_dev))

		return A304_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a305(adreno_dev))

		return A305_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a305c(adreno_dev))

		return A305C_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a306(adreno_dev))

		return A306_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a306a(adreno_dev))

		return A306A_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a310(adreno_dev))

		return A310_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a320(adreno_dev))

	if (adreno_is_a320(adreno_dev))

		return A320_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a330v2(adreno_dev))

		return A330v2_RBBM_CLOCK_CTL_DEFAULT;

		return A3XX_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a330(adreno_dev))

		return A330_RBBM_CLOCK_CTL_DEFAULT;

	else if (adreno_is_a305b(adreno_dev))

		return A305B_RBBM_CLOCK_CTL_DEFAULT;



	BUG_ON(1);

	return A3XX_RBBM_CLOCK_CTL_DEFAULT;

}



static const unsigned int _a3xx_pwron_fixup_fs_instructions[] = {

drivers/gpu/msm/adreno_ringbuffer.c

+9 −8
Original line number Diff line number Diff line
@@ -303,14 +303,15 @@ static void _ringbuffer_setup_common(struct adreno_ringbuffer *rb) 
			  ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc.gpuaddr);



	/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */

	if (adreno_is_a305(adreno_dev) || adreno_is_a305c(adreno_dev) ||

		adreno_is_a306(adreno_dev) || adreno_is_a306a(adreno_dev) ||

		adreno_is_a320(adreno_dev) ||

		adreno_is_a304(adreno_dev))

		kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x000E0602);

	else if (adreno_is_a330(adreno_dev) || adreno_is_a305b(adreno_dev) ||

			adreno_is_a310(adreno_dev))

		kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x003E2008);

	if (adreno_is_a3xx(adreno_dev)) {

		unsigned int val = 0x000E0602;



		if (adreno_is_a305b(adreno_dev) ||

				adreno_is_a310(adreno_dev) ||

				adreno_is_a330(adreno_dev))

			val = 0x003E2008;

		kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, val);

	}

}



/**