Merge "ARM: dts: msm: Add entries for dumping L1 cache for msmcobalt" (4712206e) · Commits · e / devices / android_kernel_xiaomi_markw

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+134 −3

Original line number	Diff line number	Diff line
		@@ -44,8 +44,16 @@
		L2_0: l2-cache {
		compatible = "arm,arch-cache";
		cache-level = <2>;
		qcom,dump-size = <0x0>; /* A53 L2 dump not supported */
		};
		L1_I_0: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_0: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};

		};

		CPU1: cpu@1 {
		@@ -55,6 +63,14 @@
		qcom,limits-info = <&mitigation_profile1>;
		enable-method = "psci";
		next-level-cache = <&L2_0>;
		L1_I_1: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_1: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU2: cpu@2 {
		@@ -64,6 +80,14 @@
		qcom,limits-info = <&mitigation_profile2>;
		enable-method = "psci";
		next-level-cache = <&L2_0>;
		L1_I_2: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_2: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU3: cpu@3 {
		@@ -73,6 +97,14 @@
		qcom,limits-info = <&mitigation_profile3>;
		enable-method = "psci";
		next-level-cache = <&L2_0>;
		L1_I_3: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		L1_D_3: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x9040>;
		};
		};

		CPU4: cpu@100 {
		@@ -86,6 +118,14 @@
		compatible = "arm,arch-cache";
		cache-level = <2>;
		};
		L1_I_100: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		L1_D_100: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		};

		CPU5: cpu@101 {
		@@ -95,6 +135,14 @@
		qcom,limits-info = <&mitigation_profile5>;
		enable-method = "psci";
		next-level-cache = <&L2_1>;
		L1_I_101: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		L1_D_101: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		};

		CPU6: cpu@102 {
		@@ -104,6 +152,14 @@
		qcom,limits-info = <&mitigation_profile6>;
		enable-method = "psci";
		next-level-cache = <&L2_1>;
		L1_I_102: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		L1_D_102: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		};

		CPU7: cpu@103 {
		@@ -113,6 +169,14 @@
		qcom,limits-info = <&mitigation_profile7>;
		enable-method = "psci";
		next-level-cache = <&L2_1>;
		L1_I_103: l1-icache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		L1_D_103: l1-dcache {
		compatible = "arm,arch-cache";
		qcom,dump-size = <0x12000>;
		};
		};

		cpu-map {
		@@ -1346,6 +1410,73 @@
		interrupts = <1 6 4>;
		};

		cpuss_dump {
		compatible = "qcom,cpuss-dump";
		qcom,l1_i_cache0 {
		qcom,dump-node = <&L1_I_0>;
		qcom,dump-id = <0x60>;
		};
		qcom,l1_i_cache1 {
		qcom,dump-node = <&L1_I_1>;
		qcom,dump-id = <0x61>;
		};
		qcom,l1_i_cache2 {
		qcom,dump-node = <&L1_I_2>;
		qcom,dump-id = <0x62>;
		};
		qcom,l1_i_cache3 {
		qcom,dump-node = <&L1_I_3>;
		qcom,dump-id = <0x63>;
		};
		qcom,l1_i_cache100 {
		qcom,dump-node = <&L1_I_100>;
		qcom,dump-id = <0x64>;
		};
		qcom,l1_i_cache101 {
		qcom,dump-node = <&L1_I_101>;
		qcom,dump-id = <0x65>;
		};
		qcom,l1_i_cache102 {
		qcom,dump-node = <&L1_I_102>;
		qcom,dump-id = <0x66>;
		};
		qcom,l1_i_cache103 {
		qcom,dump-node = <&L1_I_103>;
		qcom,dump-id = <0x67>;
		};
		qcom,l1_d_cache0 {
		qcom,dump-node = <&L1_D_0>;
		qcom,dump-id = <0x80>;
		};
		qcom,l1_d_cache1 {
		qcom,dump-node = <&L1_D_1>;
		qcom,dump-id = <0x81>;
		};
		qcom,l1_d_cache2 {
		qcom,dump-node = <&L1_D_2>;
		qcom,dump-id = <0x82>;
		};
		qcom,l1_d_cache3 {
		qcom,dump-node = <&L1_D_3>;
		qcom,dump-id = <0x83>;
		};
		qcom,l1_d_cache100 {
		qcom,dump-node = <&L1_D_100>;
		qcom,dump-id = <0x84>;
		};
		qcom,l1_d_cache101 {
		qcom,dump-node = <&L1_D_101>;
		qcom,dump-id = <0x85>;
		};
		qcom,l1_d_cache102 {
		qcom,dump-node = <&L1_D_102>;
		qcom,dump-id = <0x86>;
		};
		qcom,l1_d_cache103 {
		qcom,dump-node = <&L1_D_103>;
		qcom,dump-id = <0x87>;
		};
		};
		};

		&gdsc_mmss {