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Commit 46d15cc7 authored by Yaniv Rosner's avatar Yaniv Rosner Committed by David S. Miller
Browse files

bnx2x: Fix 10G mode in BCM8481/BCM84823 



Signed-off-by: default avatarYaniv Rosner <yanivr@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 93f72884

drivers/net/bnx2x_link.c

+8 −30
Original line number Diff line number Diff line
@@ -3533,8 +3533,8 @@ static void bnx2x_8481_set_10G_led_mode(struct link_params *params, 
		       MDIO_PMA_REG_8481_LINK_SIGNAL,

		       &val1);

	/* Set bit 2 to 0, and bits [1:0] to 10 */

	val1 &= ~((1<<0) | (1<<2)); /* Clear bits 0,2*/

	val1 |= (1<<1); /* Set bit 1 */

	val1 &= ~((1<<0) | (1<<2) | (1<<7)); /* Clear bits 0,2,7*/

	val1 |= ((1<<1) | (1<<6)); /* Set bit 1, 6 */



	bnx2x_cl45_write(bp, params->port,

		       ext_phy_type,
@@ -3568,36 +3568,19 @@ static void bnx2x_8481_set_10G_led_mode(struct link_params *params, 
		       MDIO_PMA_REG_8481_LED2_MASK,

		       0);



	/* LED3 (10G/1G/100/10G Activity) */

	bnx2x_cl45_read(bp, params->port,

		      ext_phy_type,

		      ext_phy_addr,

		      MDIO_PMA_DEVAD,

		      MDIO_PMA_REG_8481_LINK_SIGNAL,

		      &val1);

	/* Enable blink based on source 4(Activity) */

	val1 &= ~((1<<7) | (1<<8)); /* Clear bits 7,8 */

	val1 |= (1<<6); /* Set only bit 6 */

	/* Unmask LED3 for 10G link */

	bnx2x_cl45_write(bp, params->port,

		       ext_phy_type,

		       ext_phy_addr,

		       MDIO_PMA_DEVAD,

		       MDIO_PMA_REG_8481_LINK_SIGNAL,

		       val1);



	bnx2x_cl45_read(bp, params->port,

		       ext_phy_type,

		       ext_phy_addr,

		       MDIO_PMA_DEVAD,

		      MDIO_PMA_REG_8481_LED3_MASK,

		      &val1);

	val1 |= (1<<4); /* Unmask LED3 for 10G link */

		       0x6);

	bnx2x_cl45_write(bp, params->port,

		       ext_phy_type,

		       ext_phy_addr,

		       MDIO_PMA_DEVAD,

		       MDIO_PMA_REG_8481_LED3_MASK,

		       val1);

		       MDIO_PMA_REG_8481_LED3_BLINK,

		       0);

}
@@ -4476,17 +4459,12 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars) 
				    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {

					DP(NETIF_MSG_LINK, "Advertising 10G\n");

					/* Restart autoneg for 10G*/

			bnx2x_cl45_read(bp, params->port,

				      ext_phy_type,

				      ext_phy_addr,

				      MDIO_AN_DEVAD,

				      MDIO_AN_REG_CTRL, &val);

			val |= 0x200;



			bnx2x_cl45_write(bp, params->port,

				       ext_phy_type,

				       ext_phy_addr,

				       MDIO_AN_DEVAD,

				       MDIO_AN_REG_CTRL, val);

				       MDIO_AN_REG_CTRL, 0x3200);

				}

			} else {

				/* Force speed */

drivers/net/bnx2x_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -5129,6 +5129,7 @@ Theotherbitsarereservedandshouldbezero*/ 
#define MDIO_PMA_REG_8481_LED1_MASK	0xa82c

#define MDIO_PMA_REG_8481_LED2_MASK	0xa82f

#define MDIO_PMA_REG_8481_LED3_MASK	0xa832

#define MDIO_PMA_REG_8481_LED3_BLINK	0xa834

#define MDIO_PMA_REG_8481_SIGNAL_MASK	0xa835

#define MDIO_PMA_REG_8481_LINK_SIGNAL	0xa83b