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Commit 46ae4249 authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
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ARM: mx25: Add CLKO support 



CLKO support is a clock output on mx25 which can output many of the internal
clock sources. It is useful for debugging purpose or also for driving the
audio codec for example.

Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent d559cecc

Documentation/devicetree/bindings/clock/imx25-clock.txt

+3 −0
Original line number Diff line number Diff line
@@ -139,6 +139,9 @@ clocks and IDs. 
	uart5_ipg		124

	reserved		125

	wdt_ipg			126

	cko_div			127

	cko_sel			128

	cko			129



Examples:

arch/arm/mach-imx/clk-imx25.c

+14 −1
Original line number Diff line number Diff line
@@ -62,6 +62,10 @@ static struct clk_onecell_data clk_data; 


static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };

static const char *per_sel_clks[] = { "ahb", "upll", };

static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",

				      "ipg", "dummy", "dummy", "dummy",

				      "dummy", "dummy", "per0", "per2",

				      "per13", "per14", "usbotg_ahb", "dummy",};



enum mx25_clks {

	dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg,
@@ -82,7 +86,7 @@ enum mx25_clks { 
	pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg,

	sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg,

	uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17,

	wdt_ipg, clk_max

	wdt_ipg, cko_div, cko_sel, cko, clk_max

};



static struct clk *clk[clk_max];
@@ -117,6 +121,9 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) 
	clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));

	clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));

	clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));

	clk[cko_div] = imx_clk_divider("cko_div", "cko_sel", ccm(CCM_MCR), 24, 6);

	clk[cko_sel] = imx_clk_mux("cko_sel", ccm(CCM_MCR), 20, 4, cko_sel_clks, ARRAY_SIZE(cko_sel_clks));

	clk[cko] = imx_clk_gate("cko", "cko_div", ccm(CCM_MCR),  30);

	clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);

	clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6);

	clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6);
@@ -230,6 +237,12 @@ static int __init __mx25_clocks_init(unsigned long osc_rate) 
	clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");

	clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");



	/*

	 * Let's initially set up CLKO parent as ipg, since this configuration

	 * is used on some imx25 board designs to clock the audio codec.

	 */

	clk_set_parent(clk[cko_sel], clk[ipg]);



	return 0;

}