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Commit 469a43f8 authored by Tomer Barletz's avatar Tomer Barletz Committed by Sasha Levin
Browse files

xhci: Move xhci_pme_quirk() behind #ifdef CONFIG_PM 



commit 2b7627b73e81e5d23d5ae1490fe8e690af86e053 upstream.

xhci_pme_quirk() is only used when CONFIG_PM is defined.
Compiling a kernel without PM complains about this function

[reworded commit message -Mathias]
Signed-off-by: default avatarTomer Barletz <barletz@gmail.com>
Signed-off-by: default avatarMathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a587e280

drivers/usb/host/xhci-pci.c

+45 −45
Original line number Diff line number Diff line
@@ -174,51 +174,6 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci) 
				"QUIRK: Resetting on resume");

}



/*

 * In some Intel xHCI controllers, in order to get D3 working,

 * through a vendor specific SSIC CONFIG register at offset 0x883c,

 * SSIC PORT need to be marked as "unused" before putting xHCI

 * into D3. After D3 exit, the SSIC port need to be marked as "used".

 * Without this change, xHCI might not enter D3 state.

 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear

 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4

 */

static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend)

{

	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);

	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	u32 val;

	void __iomem *reg;



	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&

		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {



		reg = (void __iomem *) xhci->cap_regs + PORT2_SSIC_CONFIG_REG2;



		/* Notify SSIC that SSIC profile programming is not done */

		val = readl(reg) & ~PROG_DONE;

		writel(val, reg);



		/* Mark SSIC port as unused(suspend) or used(resume) */

		val = readl(reg);

		if (suspend)

			val |= SSIC_PORT_UNUSED;

		else

			val &= ~SSIC_PORT_UNUSED;

		writel(val, reg);



		/* Notify SSIC that SSIC profile programming is done */

		val = readl(reg) | PROG_DONE;

		writel(val, reg);

		readl(reg);

	}



	reg = (void __iomem *) xhci->cap_regs + 0x80a4;

	val = readl(reg);

	writel(val | BIT(28), reg);

	readl(reg);

}



#ifdef CONFIG_ACPI

static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)

{
@@ -347,6 +302,51 @@ static void xhci_pci_remove(struct pci_dev *dev) 
}



#ifdef CONFIG_PM

/*

 * In some Intel xHCI controllers, in order to get D3 working,

 * through a vendor specific SSIC CONFIG register at offset 0x883c,

 * SSIC PORT need to be marked as "unused" before putting xHCI

 * into D3. After D3 exit, the SSIC port need to be marked as "used".

 * Without this change, xHCI might not enter D3 state.

 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear

 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4

 */

static void xhci_pme_quirk(struct usb_hcd *hcd, bool suspend)

{

	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);

	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);

	u32 val;

	void __iomem *reg;



	if (pdev->vendor == PCI_VENDOR_ID_INTEL &&

		 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {



		reg = (void __iomem *) xhci->cap_regs + PORT2_SSIC_CONFIG_REG2;



		/* Notify SSIC that SSIC profile programming is not done */

		val = readl(reg) & ~PROG_DONE;

		writel(val, reg);



		/* Mark SSIC port as unused(suspend) or used(resume) */

		val = readl(reg);

		if (suspend)

			val |= SSIC_PORT_UNUSED;

		else

			val &= ~SSIC_PORT_UNUSED;

		writel(val, reg);



		/* Notify SSIC that SSIC profile programming is done */

		val = readl(reg) | PROG_DONE;

		writel(val, reg);

		readl(reg);

	}



	reg = (void __iomem *) xhci->cap_regs + 0x80a4;

	val = readl(reg);

	writel(val | BIT(28), reg);

	readl(reg);

}



static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)

{

	struct xhci_hcd	*xhci = hcd_to_xhci(hcd);