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Commit 45a252a3 authored by Dinesh K Garg's avatar Dinesh K Garg Committed by Matt Wagantall
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ARM: dts: msm: Update Qseecom driver for eMMC based ICE HW on msm8996 



eMMC based ICE (Inline Crypto Engine) requires setting of ICE specific
clocks. Updating Qseecom driver to support new ICE HW for msm8996.

Change-Id: Ia4fdd6c529f6a3c825328ba4743cdad2136d4cf8
Signed-off-by: default avatarDinesh K Garg <dineshg@codeaurora.org>
parent 56e6c59c

arch/arm/boot/dts/qcom/msm8996.dtsi

+8 −2
Original line number Diff line number Diff line
@@ -2502,7 +2502,9 @@ 
		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk",

				"ufs_core_clk_src", "ufs_core_clk",

				"ufs_bus_clk", "ufs_iface_clk";

				"ufs_bus_clk", "ufs_iface_clk",

				"sdcc_core_clk_src", "sdcc_core_clk",

				"sdcc_bus_clk", "sdcc_iface_clk";

		clocks = <&clock_gcc clk_ce1_clk>,

			 <&clock_gcc clk_qseecom_ce1_clk>,

			 <&clock_gcc clk_gcc_ce1_ahb_m_clk>,
@@ -2510,7 +2512,11 @@ 
			 <&clock_gcc clk_ufs_ice_core_clk_src>,

			 <&clock_gcc clk_gcc_ufs_ice_core_clk>,

			 <&clock_gcc clk_gcc_sys_noc_ufs_axi_clk>,

			 <&clock_gcc clk_gcc_ufs_ahb_clk>;

			 <&clock_gcc clk_gcc_ufs_ahb_clk>,

			 <&clock_gcc clk_sdcc1_ice_core_clk_src>,

			 <&clock_gcc clk_gcc_sdcc1_ice_core_clk>,

			 <&clock_gcc clk_gcc_sdcc1_ahb_clk>,

			 <&clock_gcc clk_gcc_sdcc1_apps_clk>;

		qcom,ce-opp-freq = <171430000>;

		vdd-hba-supply = <&gdsc_ufs>;

	};