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Commit 45173d5e authored by Andrew Lunn's avatar Andrew Lunn Committed by Nicolas Pitre
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ARM: Orion: mbus_dram_info consolidation



Move the *_mbus_dram_info structure into the orion platform and call it
orion_mbus_dram_info everywhere.

Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Tested-by: default avatarMichael Walle <michael@walle.cc>
Acked-by: default avatarNicolas Pitre <nico@linaro.org>
Signed-off-by: default avatarNicolas Pitre <nico@fluxnic.net>
parent b6d1c33a
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+3 −5
Original line number Diff line number Diff line
@@ -35,8 +35,6 @@
#define ATTR_PCIE_MEM		0xe8
#define ATTR_SCRATCHPAD		0x0

struct mbus_dram_target_info dove_mbus_dram_info;

static inline void __iomem *ddr_map_sc(int i)
{
	return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
@@ -102,7 +100,7 @@ void __init dove_setup_cpu_mbus(void)
	/*
	 * Setup MBUS dram target info.
	 */
	dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
	orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;

	for (i = 0, cs = 0; i < 2; i++) {
		u32 map = readl(ddr_map_sc(i));
@@ -113,7 +111,7 @@ void __init dove_setup_cpu_mbus(void)
		if (map & 1) {
			struct mbus_dram_window *w;

			w = &dove_mbus_dram_info.cs[cs++];
			w = &orion_mbus_dram_info.cs[cs++];
			w->cs_index = i;
			w->mbus_attr = 0; /* CS address decoding done inside */
					  /* the DDR controller, no need to  */
@@ -122,5 +120,5 @@ void __init dove_setup_cpu_mbus(void)
			w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
		}
	}
	dove_mbus_dram_info.num_cs = cs;
	orion_mbus_dram_info.num_cs = cs;
}
+6 −5
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@
#include <linux/irq.h>
#include <plat/time.h>
#include <plat/common.h>
#include <plat/addr-map.h>
#include "common.h"

static int get_tclk(void);
@@ -71,7 +72,7 @@ void __init dove_map_io(void)
 ****************************************************************************/
void __init dove_ehci0_init(void)
{
	orion_ehci_init(&dove_mbus_dram_info,
	orion_ehci_init(&orion_mbus_dram_info,
			DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
}

@@ -80,7 +81,7 @@ void __init dove_ehci0_init(void)
 ****************************************************************************/
void __init dove_ehci1_init(void)
{
	orion_ehci_1_init(&dove_mbus_dram_info,
	orion_ehci_1_init(&orion_mbus_dram_info,
			  DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
}

@@ -89,7 +90,7 @@ void __init dove_ehci1_init(void)
 ****************************************************************************/
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
	orion_ge00_init(eth_data, &dove_mbus_dram_info,
	orion_ge00_init(eth_data, &orion_mbus_dram_info,
			DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
			0, get_tclk());
}
@@ -107,7 +108,7 @@ void __init dove_rtc_init(void)
 ****************************************************************************/
void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
	orion_sata_init(sata_data, &dove_mbus_dram_info,
	orion_sata_init(sata_data, &orion_mbus_dram_info,
			DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);

}
@@ -198,7 +199,7 @@ struct sys_timer dove_timer = {
 ****************************************************************************/
void __init dove_xor0_init(void)
{
	orion_xor0_init(&dove_mbus_dram_info,
	orion_xor0_init(&orion_mbus_dram_info,
			DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
			IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
}
+0 −1
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ struct mv643xx_eth_platform_data;
struct mv_sata_platform_data;

extern struct sys_timer dove_timer;
extern struct mbus_dram_target_info dove_mbus_dram_info;

/*
 * Basic Dove init functions used early by machine-setup.
+2 −1
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@
#include <plat/pcie.h>
#include <mach/irqs.h>
#include <mach/bridge-regs.h>
#include <plat/addr-map.h>
#include "common.h"

struct pcie_port {
@@ -50,7 +51,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
	 */
	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);

	orion_pcie_setup(pp->base, &dove_mbus_dram_info);
	orion_pcie_setup(pp->base, &orion_mbus_dram_info);

	/*
	 * IORESOURCE_IO
+1 −4
Original line number Diff line number Diff line
@@ -35,8 +35,6 @@
#define ATTR_PCIE1_MEM		0xd8
#define ATTR_SRAM		0x01

struct mbus_dram_target_info kirkwood_mbus_dram_info;

/*
 * Description of the windows needed by the platform code
 */
@@ -88,6 +86,5 @@ void __init kirkwood_setup_cpu_mbus(void)
	/*
	 * Setup MBUS dram target info.
	 */
	orion_setup_cpu_mbus_target(&addr_map_cfg, &kirkwood_mbus_dram_info,
				    DDR_WINDOW_CPU_BASE);
	orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
}
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