arm64: gicv3: Insert barriers after SGI operations

Some early samples of the MSMTHULIUM SoC require that two
successive writes to the ICC_SGI1R_EL1 register be
separated by a barrier instruction. Implement a Kconfig
option to enable this behavior if necessary.

Change-Id: I830f5a6db3f21c8e0a9cf2815b602dc56eac7598
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>