Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4507cc73 authored by Stepan Moskovchenko's avatar Stepan Moskovchenko Committed by Matt Wagantall
Browse files

arm64: gicv3: Insert barriers after SGI operations 



Some early samples of the MSMTHULIUM SoC require that two
successive writes to the ICC_SGI1R_EL1 register be
separated by a barrier instruction. Implement a Kconfig
option to enable this behavior if necessary.

Change-Id: I830f5a6db3f21c8e0a9cf2815b602dc56eac7598
Signed-off-by: default avatarStepan Moskovchenko <stepanm@codeaurora.org>
parent 20a22bfd

drivers/irqchip/Kconfig

+12 −0
Original line number Diff line number Diff line
@@ -54,6 +54,18 @@ config BRCMSTB_L2_IRQ 
	select GENERIC_IRQ_CHIP

	select IRQ_DOMAIN



config MSM_GIC_SGI_NEEDS_BARRIER

	bool "SGI operations require explicit barriers"

	depends on ARM_GIC_V3

	def_bool ARCH_MSMTHULIUM

	help

	  Some early samples of the MSMTHULIUM SoCs require that an explicit

	  barrier be executed between two sucessive writes to the ICC_SGI1R_EL1

	  register. If you are building the kernel to work on one of these early

	  designs, select 'Y' here.



	  For production kernels, you should say 'N' here.



config DW_APB_ICTL

	bool

	select IRQ_DOMAIN

drivers/irqchip/irq-gic-v3.c

+10 −0
Original line number Diff line number Diff line
@@ -138,7 +138,17 @@ static void __maybe_unused gic_write_grpen1(u64 val) 


static void __maybe_unused gic_write_sgi1r(u64 val)

{

#ifdef CONFIG_MSM_GIC_SGI_NEEDS_BARRIER

	static DEFINE_RAW_SPINLOCK(sgi_lock);

	unsigned long flags;

	raw_spin_lock_irqsave(&sgi_lock, flags);

#endif



	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));

#ifdef CONFIG_MSM_GIC_SGI_NEEDS_BARRIER

	dsb(nsh);

	raw_spin_unlock_irqrestore(&sgi_lock, flags);

#endif

}



static void gic_enable_sre(void)