Loading arch/arm/boot/dts/qcom/mdm9607-pinctrl.dtsi +26 −0 Original line number Diff line number Diff line Loading @@ -61,6 +61,32 @@ }; }; blsp1_uart5_active: blsp1_uart5_active { mux { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "blsp_uart5"; }; config { pins = "gpio8", "gpio9", "gpio10", "gpio11"; drive-strength = <2>; bias-disable; }; }; blsp1_uart5_sleep: blsp1_uart5_sleep { mux { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "gpio"; }; config { pins = "gpio8", "gpio9", "gpio10", "gpio11"; drive-strength = <2>; bias-disable; }; }; spi1 { spi1_default: spi1_default { Loading arch/arm/boot/dts/qcom/mdm9607.dtsi +37 −0 Original line number Diff line number Diff line Loading @@ -577,6 +577,43 @@ status = "disabled"; }; blsp1_uart5_hs: uart@78b3000 { /* BLSP1 UART5 */ compatible = "qcom,msm-hsuart-v14"; reg = <0x78b3000 0x200>, <0x7884000 0x23000>; reg-names = "core_mem", "bam_mem"; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart5_hs>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 121 0 1 &intc 0 238 0 2 &tlmm_pinmux 9 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xFD>; qcom,bam-tx-ep-pipe-index = <8>; qcom,bam-rx-ep-pipe-index = <9>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; clocks = <&clock_gcc clk_gcc_blsp1_uart5_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart5_sleep>; pinctrl-1 = <&blsp1_uart5_active>; qcom,msm-bus,name = "buart5"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <86 512 0 0>, <86 512 500 800>; status = "disabled"; }; cnss_sdio: qcom,cnss-sdio { compatible = "qcom,cnss_sdio"; reg = <0x87a00000 0x200000>; Loading Loading
arch/arm/boot/dts/qcom/mdm9607-pinctrl.dtsi +26 −0 Original line number Diff line number Diff line Loading @@ -61,6 +61,32 @@ }; }; blsp1_uart5_active: blsp1_uart5_active { mux { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "blsp_uart5"; }; config { pins = "gpio8", "gpio9", "gpio10", "gpio11"; drive-strength = <2>; bias-disable; }; }; blsp1_uart5_sleep: blsp1_uart5_sleep { mux { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "gpio"; }; config { pins = "gpio8", "gpio9", "gpio10", "gpio11"; drive-strength = <2>; bias-disable; }; }; spi1 { spi1_default: spi1_default { Loading
arch/arm/boot/dts/qcom/mdm9607.dtsi +37 −0 Original line number Diff line number Diff line Loading @@ -577,6 +577,43 @@ status = "disabled"; }; blsp1_uart5_hs: uart@78b3000 { /* BLSP1 UART5 */ compatible = "qcom,msm-hsuart-v14"; reg = <0x78b3000 0x200>, <0x7884000 0x23000>; reg-names = "core_mem", "bam_mem"; interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; #address-cells = <0>; interrupt-parent = <&blsp1_uart5_hs>; interrupts = <0 1 2>; #interrupt-cells = <1>; interrupt-map-mask = <0xffffffff>; interrupt-map = <0 &intc 0 121 0 1 &intc 0 238 0 2 &tlmm_pinmux 9 0>; qcom,inject-rx-on-wakeup; qcom,rx-char-to-inject = <0xFD>; qcom,bam-tx-ep-pipe-index = <8>; qcom,bam-rx-ep-pipe-index = <9>; qcom,master-id = <86>; clock-names = "core_clk", "iface_clk"; clocks = <&clock_gcc clk_gcc_blsp1_uart5_apps_clk>, <&clock_gcc clk_gcc_blsp1_ahb_clk>; pinctrl-names = "sleep", "default"; pinctrl-0 = <&blsp1_uart5_sleep>; pinctrl-1 = <&blsp1_uart5_active>; qcom,msm-bus,name = "buart5"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <86 512 0 0>, <86 512 500 800>; status = "disabled"; }; cnss_sdio: qcom,cnss-sdio { compatible = "qcom,cnss_sdio"; reg = <0x87a00000 0x200000>; Loading