Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4457af67 authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
Browse files

MIPS: perf: Fix build failure in XLP perf support. 



Commit 4be3d2f3 ("MIPS: perf: Add XLP
support for hardware perf.") added UNSUPPORTED_PERF_EVENT_ID which was
removed a while back.

Cc: Zi Shen Lim <zlim@netlogicmicro.com>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: Zi Shen Lim <zlim@netlogicmicro.com>
Signed-off-by: default avatarManuel Lauss <manuel.lauss@gmail.com>
Acked-by: default avatarJayachandran C <jchandra@broadcom.com>
Patchwork: https://patchwork.linux-mips.org/patch/4730/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8e0d7372

arch/mips/kernel/perf_event_mipsxx.c

+0 −38
Original line number Diff line number Diff line
@@ -847,7 +847,6 @@ static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = { 
	[PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */

	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */

	[PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },

};



/* 24K/34K/1004K cores can share the same cache event map. */
@@ -1115,24 +1114,12 @@ static const struct mips_perf_event xlp_cache_map 
		[C(RESULT_ACCESS)]	= { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */

		[C(RESULT_MISS)]	= { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },

	},

},

[C(L1I)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)]	= { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */

		[C(RESULT_MISS)]	= { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },

	},

},

[C(LL)] = {

	[C(OP_READ)] = {
@@ -1143,10 +1130,6 @@ static const struct mips_perf_event xlp_cache_map 
		[C(RESULT_ACCESS)]	= { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */

		[C(RESULT_MISS)]	= { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },

	},

},

[C(DTLB)] = {

	/*
@@ -1154,45 +1137,24 @@ static const struct mips_perf_event xlp_cache_map 
	 * read and write.

	 */

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },

	},

},

[C(ITLB)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },

	},

},

[C(BPU)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { 0x25, CNTR_ALL },

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },

	},

	[C(OP_PREFETCH)] = {

		[C(RESULT_ACCESS)]	= { UNSUPPORTED_PERF_EVENT_ID },

		[C(RESULT_MISS)]	= { UNSUPPORTED_PERF_EVENT_ID },

	},

},

};