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Commit 440a7cd8 authored by Jerome Glisse's avatar Jerome Glisse Committed by Dave Airlie
Browse files

drm/radeon: improve GPU lockup debugging info on r6xx/r7xx/r8xx/r9xx 



Print various CP register that have valuable informations regarding
GPU lockup.

Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 4dbdf0ae

drivers/gpu/drm/radeon/evergreen.c

+16 −0
Original line number Diff line number Diff line
@@ -2316,6 +2316,14 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(GRBM_STATUS_SE1));

	dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",

		RREG32(SRBM_STATUS));

	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",

		RREG32(CP_STALLED_STAT1));

	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",

		RREG32(CP_STALLED_STAT2));

	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",

		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

	evergreen_mc_stop(rdev, &save);

	if (evergreen_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
@@ -2353,6 +2361,14 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(GRBM_STATUS_SE1));

	dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",

		RREG32(SRBM_STATUS));

	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",

		RREG32(CP_STALLED_STAT1));

	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",

		RREG32(CP_STALLED_STAT2));

	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",

		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

	evergreen_mc_resume(rdev, &save);

	return 0;

}

drivers/gpu/drm/radeon/evergreend.h

+4 −0
Original line number Diff line number Diff line
@@ -88,6 +88,10 @@ 
#define	CONFIG_MEMSIZE					0x5428



#define	CP_COHER_BASE					0x85F8

#define	CP_STALLED_STAT1			0x8674

#define	CP_STALLED_STAT2			0x8678

#define	CP_BUSY_STAT				0x867C

#define	CP_STAT						0x8680

#define CP_ME_CNTL					0x86D8

#define		CP_ME_HALT					(1 << 28)

#define		CP_PFP_HALT					(1 << 26)

drivers/gpu/drm/radeon/ni.c

+16 −0
Original line number Diff line number Diff line
@@ -1122,6 +1122,14 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(GRBM_STATUS_SE1));

	dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",

		RREG32(SRBM_STATUS));

	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",

		RREG32(CP_STALLED_STAT1));

	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",

		RREG32(CP_STALLED_STAT2));

	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",

		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",

		 RREG32(0x14F8));

	dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
@@ -1170,6 +1178,14 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(GRBM_STATUS_SE1));

	dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",

		RREG32(SRBM_STATUS));

	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",

		RREG32(CP_STALLED_STAT1));

	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",

		RREG32(CP_STALLED_STAT2));

	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",

		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

	evergreen_mc_resume(rdev, &save);

	return 0;

}

drivers/gpu/drm/radeon/nid.h

+4 −0
Original line number Diff line number Diff line
@@ -236,6 +236,10 @@ 
#define	CP_SEM_WAIT_TIMER				0x85BC

#define	CP_SEM_INCOMPLETE_TIMER_CNTL			0x85C8

#define	CP_COHER_CNTL2					0x85E8

#define	CP_STALLED_STAT1			0x8674

#define	CP_STALLED_STAT2			0x8678

#define	CP_BUSY_STAT				0x867C

#define	CP_STAT						0x8680

#define CP_ME_CNTL					0x86D8

#define		CP_ME_HALT					(1 << 28)

#define		CP_PFP_HALT					(1 << 26)

drivers/gpu/drm/radeon/r600.c

+16 −0
Original line number Diff line number Diff line
@@ -1289,6 +1289,14 @@ int r600_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(R_008014_GRBM_STATUS2));

	dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",

		RREG32(R_000E50_SRBM_STATUS));

	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",

		RREG32(CP_STALLED_STAT1));

	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",

		RREG32(CP_STALLED_STAT2));

	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",

		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

	rv515_mc_stop(rdev, &save);

	if (r600_mc_wait_for_idle(rdev)) {

		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
@@ -1332,6 +1340,14 @@ int r600_gpu_soft_reset(struct radeon_device *rdev) 
		RREG32(R_008014_GRBM_STATUS2));

	dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",

		RREG32(R_000E50_SRBM_STATUS));

	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",

		RREG32(CP_STALLED_STAT1));

	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",

		RREG32(CP_STALLED_STAT2));

	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",

		RREG32(CP_BUSY_STAT));

	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",

		RREG32(CP_STAT));

	rv515_mc_resume(rdev, &save);

	return 0;

}