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Commit 43e8e103 authored by Pushkar Joshi's avatar Pushkar Joshi
Browse files

ARM: dts: msm: Add GCC and MMSS GDSCs for MSMCOBALT 



Add the GDSC devices for all GCC GDSCs, except the votable GDSCs and
most MMSS GDSCs. Keep using the dummy GDSC devices for the remaining
ones since the current simulation builds do not model them.

Also add support for dummy gpu clock controller.

Change-Id: I81f215b95f6ad16eda99834817eed0d090415a7d
Signed-off-by: default avatarPushkar Joshi <pushkarj@codeaurora.org>
parent 7f8441ae

arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi

+15 −13
Original line number Diff line number Diff line
@@ -14,28 +14,28 @@ 
&soc {

	/* GCC GDSCs */

	gdsc_mmss: qcom,gdsc@109004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_mmss";

		reg = <0x109004 0x4>;

		status = "disabled";

	};



	gdsc_usb30: qcom,gdsc@10f004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_usb30";

		reg = <0x10f004 0x4>;

		status = "disabled";

	};



	gdsc_pcie_0: qcom,gdsc@16b004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_pcie_0";

		reg = <0x16b004 0x4>;

		status = "disabled";

	};



	gdsc_ufs: qcom,gdsc@175004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_ufs";

		reg = <0x175004 0x4>;

		status = "disabled";
@@ -74,56 +74,56 @@ 
	};



	gdsc_venus: qcom,gdsc@c8c1024 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_venus";

		reg = <0xc8c1024 0x4>;

		status = "disabled";

	};



	gdsc_venus_core0: qcom,gdsc@c8c1040 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_venus_core0";

		reg = <0xc8c1040 0x4>;

		status = "disabled";

	};



	gdsc_venus_core1: qcom,gdsc@c8c1044 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_venus_core1";

		reg = <0xc8c1044 0x4>;

		status = "disabled";

	};



	gdsc_camss_top: qcom,gdsc@c8c34a0 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_camss_top";

		reg = <0xc8c34a0 0x4>;

		status = "disabled";

	};



	gdsc_vfe0: qcom,gdsc@c8c3664 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_vfe0";

		reg = <0xc8c3664 0x4>;

		status = "disabled";

	};



	gdsc_vfe1: qcom,gdsc@c8c3674 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_vfe1";

		reg = <0xc8c3674 0x4>;

		status = "disabled";

	};



	gdsc_cpp: qcom,gdsc@c8c36d4 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_cpp";

		reg = <0xc8c36d4 0x4>;

		status = "disabled";

	};



	gdsc_mdss: qcom,gdsc@c8c2304 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "gdsc_mdss";

		reg = <0xc8c2304 0x4>;

		status = "disabled";
@@ -133,7 +133,9 @@ 
	gdsc_gpu_cx: qcom,gdsc@5066004 {

		compatible = "regulator-fixed";

		regulator-name = "gdsc_gpu_cx";

		reg = <0x5066004 0x4>;

		reg = <0x5066004 0x4>,

		      <0x5065130 0x4>;

		reg-names = "base", "domain_addr";

		status = "disabled";

	};

arch/arm/boot/dts/qcom/msmcobalt.dtsi

+49 −0
Original line number Diff line number Diff line
@@ -292,6 +292,11 @@ 
		#clock-cells = <1>;

	};



	clock_gpu: qcom,gpucc@5065000 {

		compatible = "qcom,dummycc";

		#clock-cells = <1>;

	};



	clock_debug: qcom,debugcc@162000 {

		compatible = "qcom,dummycc";

		#clock-cells = <1>;
@@ -591,18 +596,30 @@ 
};



&gdsc_usb30 {

	clock-names = "core_clk";

	clocks = <&clock_gcc clk_gcc_usb30_master_clk>;

	status = "ok";

};



&gdsc_pcie_0 {

	clock-names = "master_bus_clk", "slave_bus_clk", "core_clk";

	clocks = <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>,

		 <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>,

		 <&clock_gcc clk_gcc_pcie_0_pipe_clk>;

	status = "ok";

};



&gdsc_ufs {

	clock-names = "bus_clk", "ice_clk", "unipro_clk";

	clocks = <&clock_gcc clk_gcc_ufs_axi_clk>,

		 <&clock_gcc clk_gcc_ufs_ice_core_clk>,

		 <&clock_gcc clk_gcc_ufs_unipro_core_clk>;

	status = "ok";

};



&gdsc_bimc_smmu {

	clock-names = "bus_clk";

	clocks = <&clock_gcc clk_bimc_smmu_axi_clk>;

	status = "ok";

};
@@ -619,38 +636,70 @@ 
};



&gdsc_venus {

	clock-names = "bus_clk", "maxi_clk", "core_clk";

	clocks = <&clock_mmss clk_video_axi_clk>,

		 <&clock_mmss clk_video_maxi_clk>,

		 <&clock_mmss clk_video_core_clk>;

	status = "ok";

};



&gdsc_venus_core0 {

	clock-names = "core0_clk";

	clocks = <&clock_mmss clk_video_subcore0_clk>;

	status = "ok";

};



&gdsc_venus_core1 {

	clock-names = "core1_clk";

	clocks = <&clock_mmss clk_video_subcore1_clk>;

	status = "ok";

};



&gdsc_camss_top {

	clock-names = "bus_clk", "vfe_axi";

	clocks = <&clock_mmss clk_camss_cpp_axi_clk>,

		 <&clock_mmss clk_camss_vfe_vbif_axi_clk>;

	status = "ok";

};



&gdsc_vfe0 {

	clock-names = "core0_clk" , "core0_stream_clk";

	clocks = <&clock_mmss clk_camss_vfe0_clk>,

		 <&clock_mmss clk_camss_vfe0_stream_clk>;

	parent-supply = <&gdsc_camss_top>;

	status = "ok";

};



&gdsc_vfe1 {

	clock-names = "core1_clk" , "core1_stream_clk";

	clocks = <&clock_mmss clk_camss_vfe1_clk>,

		 <&clock_mmss clk_camss_vfe1_stream_clk>;

	parent-supply = <&gdsc_camss_top>;

	status = "ok";

};



&gdsc_cpp {

	clock-names = "core_clk";

	clocks = <&clock_mmss clk_camss_cpp_clk>;

	parent-supply = <&gdsc_camss_top>;

	status = "ok";

};



&gdsc_mdss {

	clock-names = "bus_clk", "core_clk", "root_clk";

	clocks = <&clock_mmss clk_mdss_axi_clk>,

		 <&clock_mmss clk_mdss_mdp_clk>,

		 <&clock_mmss clk_mdss_rot_clk>;

	status = "ok";

};



&gdsc_gpu_gx {

	clock-names = "bimc_core_clk", "core_clk", "core_root_clk";

	clocks = <&clock_gcc clk_gcc_gpu_bimc_gfx_clk>,

		 <&clock_gpu clk_gfx3d_clk>,

		 <&clock_gpu clk_gfx3d_clk_src>;

	qcom,force-enable-root-clk;

	parent-supply = <&pm8005_s1>;

	status = "ok";

};