Commit 43bac783 authored Oct 20, 2015 by Jaydeep Sen

clk: msm: mdmfermium: Add support for 25MHz in emac_0_sys_25m_clk_src



SGMI driver needs support for 25 MHz in emac_0_sys_25m_clk_src. Use
125 MHz emac source PLL to derive rate of 25 MHz using divider.

Change-Id: Ibc74d43cc97974ca01177ff09575e0ce168949c3
Signed-off-by: Jaydeep Sen <jsen@codeaurora.org>

parent 41747adc

drivers/clk/msm/clock-gcc-mdmfermium.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -226,6 +226,7 @@ static struct rcg_clk emac_0_125m_clk_src = {

		static struct clk_freq_tbl ftbl_emac_0_sys_25m_clk_src[] = {
		F( 19200000, xo, 1, 0, 0),
		F_EXT( 25000000, emac_0_125m_clk, 5, 0, 0),
		F_EXT( 125000000, emac_0_125m_clk, 1, 0, 0),
		F_END
		};