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Commit 438a8706 authored by Charan Teja Reddy's avatar Charan Teja Reddy
Browse files

ARM: dts: msm: enable the etm registers save-restore on MSM8953 



Enable the ETM save-restore logic that is used to context save of
CPU-ETM registers across the power collapse.

Change-Id: Ief20ce33741f514ec99b79aefb36cf9c7af842d0
Signed-off-by: default avatarCharan Teja Reddy <charante@codeaurora.org>
parent 97df2c0e

arch/arm/boot/dts/qcom/msm8953.dtsi

+0 −8
Original line number Diff line number Diff line
@@ -1198,7 +1198,6 @@ 
		      <0x6190000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,save-restore-disable;

		qcom,coresight-jtagmm-cpu = <&CPU0>;



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -1212,7 +1211,6 @@ 
		      <0x6192000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,save-restore-disable;

		qcom,coresight-jtagmm-cpu = <&CPU1>;



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -1226,7 +1224,6 @@ 
		      <0x6194000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,save-restore-disable;

		qcom,coresight-jtagmm-cpu = <&CPU2>;



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -1240,7 +1237,6 @@ 
		      <0x6196000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,save-restore-disable;

		qcom,coresight-jtagmm-cpu = <&CPU3>;



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -1254,7 +1250,6 @@ 
		      <0x61b0000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,save-restore-disable;

		qcom,coresight-jtagmm-cpu = <&CPU4>;



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -1268,7 +1263,6 @@ 
		      <0x61b2000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,save-restore-disable;

		qcom,coresight-jtagmm-cpu = <&CPU5>;



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -1282,7 +1276,6 @@ 
		      <0x61b4000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,save-restore-disable;

		qcom,coresight-jtagmm-cpu = <&CPU6>;



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -1296,7 +1289,6 @@ 
		      <0x61b6000 0x1000>;

		reg-names = "etm-base", "debug-base";



		qcom,save-restore-disable;

		qcom,coresight-jtagmm-cpu = <&CPU7>;



		clocks = <&clock_gcc clk_qdss_clk>,