Loading arch/mips/kernel/traps.c +6 −2 Original line number Diff line number Diff line Loading @@ -1582,7 +1582,11 @@ void __init set_handler(unsigned long offset, void *addr, unsigned long size) static char panic_null_cerr[] __cpuinitdata = "Trying to set NULL cache error exception handler"; /* Install uncached CPU exception handler */ /* * Install uncached CPU exception handler. * This is suitable only for the cache error exception which is the only * exception handler that is being run uncached. */ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { Loading @@ -1593,7 +1597,7 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, unsigned long uncached_ebase = TO_UNCAC(ebase); #endif if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); uncached_ebase += (read_c0_ebase() & 0x3ffff000); if (!addr) panic(panic_null_cerr); Loading Loading
arch/mips/kernel/traps.c +6 −2 Original line number Diff line number Diff line Loading @@ -1582,7 +1582,11 @@ void __init set_handler(unsigned long offset, void *addr, unsigned long size) static char panic_null_cerr[] __cpuinitdata = "Trying to set NULL cache error exception handler"; /* Install uncached CPU exception handler */ /* * Install uncached CPU exception handler. * This is suitable only for the cache error exception which is the only * exception handler that is being run uncached. */ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { Loading @@ -1593,7 +1597,7 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr, unsigned long uncached_ebase = TO_UNCAC(ebase); #endif if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); uncached_ebase += (read_c0_ebase() & 0x3ffff000); if (!addr) panic(panic_null_cerr); Loading