Commit 42baf21d authored Sep 18, 2013 by Michel Dänzer Committed by Alex Deucher Sep 20, 2013

drm/radeon/cik: Add tiling mode index for 1D tiled depth/stencil surfaces



CIK uses a different index for 1D DST surfaces compared to SI.  Expose
the new index so libdrm_radeon can use it properly for userspace
drivers.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent a537314e

include/uapi/drm/radeon_drm.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -1007,4 +1007,6 @@ struct drm_radeon_info {
		#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
		#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2

		#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5

		#endif