Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 42a11179 authored by Tony Wu's avatar Tony Wu Committed by Ralf Baechle
Browse files

MIPS: Fix typos and cleanup comment 



Signed-off-by: default avatarTony Wu <tung7970@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5535/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent fc192e50

arch/mips/include/asm/gic.h

+1 −1
Original line number Diff line number Diff line
@@ -347,7 +347,7 @@ struct gic_shared_intr_map { 
#define GIC_CPU_INT2		2 /* .		      */

#define GIC_CPU_INT3		3 /* .		      */

#define GIC_CPU_INT4		4 /* .		      */

#define GIC_CPU_INT5		5 /* Core Interrupt 5 */

#define GIC_CPU_INT5		5 /* Core Interrupt 7 */



/* Local GIC interrupts. */

#define GIC_INT_TMR		(GIC_CPU_INT5)

arch/mips/kernel/process.c

+0 −3
Original line number Diff line number Diff line
@@ -207,9 +207,6 @@ unsigned long __stack_chk_guard __read_mostly; 
EXPORT_SYMBOL(__stack_chk_guard);

#endif



/*

 *

 */

struct mips_frame_info {

	void		*func;

	unsigned long	func_size;

arch/mips/mm/tlbex.c

+1 −1
Original line number Diff line number Diff line
@@ -972,7 +972,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 
	uasm_i_srl(p, ptr, ptr, 19);

#else

	/*

	 * smp_processor_id() << 3 is stored in CONTEXT.

	 * smp_processor_id() << 2 is stored in CONTEXT.

	 */

	uasm_i_mfc0(p, ptr, C0_CONTEXT);

	UASM_i_LA_mostly(p, tmp, pgdc);