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Commit 423e38e8 authored by Rajkumar Manoharan's avatar Rajkumar Manoharan Committed by John W. Linville
Browse files

ath9k: Rename AR9480 into AR9462 



Renamed to be in sync with Marketing term and to avoid
confusion with other chip names.

Signed-off-by: default avatarRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 76db2f8c

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

+9 −9
Original line number Diff line number Diff line
@@ -3556,7 +3556,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) 


	if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))

		REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);

	else if (AR_SREV_9480(ah))

	else if (AR_SREV_9462(ah))

		REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);

	else {

		REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
@@ -3635,20 +3635,20 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 


	u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);



	if (AR_SREV_9480(ah)) {

		if (AR_SREV_9480_10(ah)) {

	if (AR_SREV_9462(ah)) {

		if (AR_SREV_9462_10(ah)) {

			value &= ~AR_SWITCH_TABLE_COM_SPDT;

			value |= 0x00100000;

		}

		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,

				AR_SWITCH_TABLE_COM_AR9480_ALL, value);

				AR_SWITCH_TABLE_COM_AR9462_ALL, value);

	} else

		REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,

			      AR_SWITCH_TABLE_COM_ALL, value);





	/*

	 *   AR9480 defines new switch table for BT/WLAN,

	 *   AR9462 defines new switch table for BT/WLAN,

	 *       here's new field name in XXX.ref for both 2G and 5G.

	 *   Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)

	 *   15:12   R/W     SWITCH_TABLE_COM_SPDT_WLAN_RX
@@ -3660,7 +3660,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 
	 *   7:4 R/W  SWITCH_TABLE_COM_SPDT_WLAN_IDLE

	 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE

	 */

	if (AR_SREV_9480_20_OR_LATER(ah)) {

	if (AR_SREV_9462_20_OR_LATER(ah)) {

		value = ar9003_switch_com_spdt_get(ah, is2ghz);

		REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,

				AR_SWITCH_TABLE_COM_SPDT_ALL, value);
@@ -3909,7 +3909,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) 
			REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);

			if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))

				return;

		} else if (AR_SREV_9480(ah)) {

		} else if (AR_SREV_9462(ah)) {

			reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);

			REG_WRITE(ah, AR_PHY_PMU1, reg_val);

		} else {
@@ -3940,7 +3940,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) 
			while (!REG_READ_FIELD(ah, AR_PHY_PMU2,

						AR_PHY_PMU2_PGM))

				udelay(10);

		} else if (AR_SREV_9480(ah))

		} else if (AR_SREV_9462(ah))

			REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);

		else {

			reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
@@ -4527,7 +4527,7 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah, 


	REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);



	if (AR_SREV_9480_20(ah))

	if (AR_SREV_9462_20(ah))

		REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,

			      AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);

drivers/net/wireless/ath/ath9k/ar9003_hw.c

+91 −91
Original line number Diff line number Diff line
@@ -35,13 +35,13 @@ 
static void ar9003_hw_init_mode_regs(struct ath_hw *ah)

{

#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \

		ar9480_pciephy_pll_on_clkreq_disable_L1_2p0

		ar9462_pciephy_pll_on_clkreq_disable_L1_2p0



#define AR9480_BB_CTX_COEFJ(x)	\

		ar9480_##x##_baseband_core_txfir_coeff_japan_2484

#define AR9462_BB_CTX_COEFJ(x)	\

		ar9462_##x##_baseband_core_txfir_coeff_japan_2484



#define AR9480_BBC_TXIFR_COEFFJ \

		ar9480_2p0_baseband_core_txfir_coeff_japan_2484

#define AR9462_BBC_TXIFR_COEFFJ \

		ar9462_2p0_baseband_core_txfir_coeff_japan_2484

	if (AR_SREV_9330_11(ah)) {

		/* mac */

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
@@ -264,107 +264,107 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 
				ar9485_1_1_pcie_phy_clkreq_disable_L1,

				ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),

				2);

	} else if (AR_SREV_9480_10(ah)) {

	} else if (AR_SREV_9462_10(ah)) {

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9480_1p0_mac_core,

				ARRAY_SIZE(ar9480_1p0_mac_core), 2);

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_1p0_mac_core,

				ARRAY_SIZE(ar9462_1p0_mac_core), 2);

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],

				ar9480_1p0_mac_postamble,

				ARRAY_SIZE(ar9480_1p0_mac_postamble),

				ar9462_1p0_mac_postamble,

				ARRAY_SIZE(ar9462_1p0_mac_postamble),

				5);



		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],

				ar9480_1p0_baseband_core,

				ARRAY_SIZE(ar9480_1p0_baseband_core),

				ar9462_1p0_baseband_core,

				ARRAY_SIZE(ar9462_1p0_baseband_core),

				2);

		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],

				ar9480_1p0_baseband_postamble,

				ARRAY_SIZE(ar9480_1p0_baseband_postamble), 5);

				ar9462_1p0_baseband_postamble,

				ARRAY_SIZE(ar9462_1p0_baseband_postamble), 5);



		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],

				ar9480_1p0_radio_core,

				ARRAY_SIZE(ar9480_1p0_radio_core), 2);

				ar9462_1p0_radio_core,

				ARRAY_SIZE(ar9462_1p0_radio_core), 2);

		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],

				ar9480_1p0_radio_postamble,

				ARRAY_SIZE(ar9480_1p0_radio_postamble), 5);

				ar9462_1p0_radio_postamble,

				ARRAY_SIZE(ar9462_1p0_radio_postamble), 5);



		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],

				ar9480_1p0_soc_preamble,

				ARRAY_SIZE(ar9480_1p0_soc_preamble), 2);

				ar9462_1p0_soc_preamble,

				ARRAY_SIZE(ar9462_1p0_soc_preamble), 2);

		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],

				ar9480_1p0_soc_postamble,

				ARRAY_SIZE(ar9480_1p0_soc_postamble), 5);

				ar9462_1p0_soc_postamble,

				ARRAY_SIZE(ar9462_1p0_soc_postamble), 5);



		INIT_INI_ARRAY(&ah->iniModesRxGain,

				ar9480_common_rx_gain_table_1p0,

				ARRAY_SIZE(ar9480_common_rx_gain_table_1p0), 2);

				ar9462_common_rx_gain_table_1p0,

				ARRAY_SIZE(ar9462_common_rx_gain_table_1p0), 2);



		/* Awake -> Sleep Setting */

		INIT_INI_ARRAY(&ah->iniPcieSerdes,

			ar9480_pcie_phy_clkreq_disable_L1_1p0,

			ARRAY_SIZE(ar9480_pcie_phy_clkreq_disable_L1_1p0),

			ar9462_pcie_phy_clkreq_disable_L1_1p0,

			ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),

			2);



		/* Sleep -> Awake Setting */

		INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,

			ar9480_pcie_phy_clkreq_disable_L1_1p0,

			ARRAY_SIZE(ar9480_pcie_phy_clkreq_disable_L1_1p0),

			ar9462_pcie_phy_clkreq_disable_L1_1p0,

			ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),

			2);



		INIT_INI_ARRAY(&ah->iniModesAdditional,

				ar9480_modes_fast_clock_1p0,

				ARRAY_SIZE(ar9480_modes_fast_clock_1p0), 3);

				ar9462_modes_fast_clock_1p0,

				ARRAY_SIZE(ar9462_modes_fast_clock_1p0), 3);

		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

				AR9480_BB_CTX_COEFJ(1p0),

				ARRAY_SIZE(AR9480_BB_CTX_COEFJ(1p0)), 2);

				AR9462_BB_CTX_COEFJ(1p0),

				ARRAY_SIZE(AR9462_BB_CTX_COEFJ(1p0)), 2);



	} else if (AR_SREV_9480_20(ah)) {

	} else if (AR_SREV_9462_20(ah)) {



		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9480_2p0_mac_core,

				ARRAY_SIZE(ar9480_2p0_mac_core), 2);

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,

				ARRAY_SIZE(ar9462_2p0_mac_core), 2);

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],

				ar9480_2p0_mac_postamble,

				ARRAY_SIZE(ar9480_2p0_mac_postamble), 5);

				ar9462_2p0_mac_postamble,

				ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);



		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],

				ar9480_2p0_baseband_core,

				ARRAY_SIZE(ar9480_2p0_baseband_core), 2);

				ar9462_2p0_baseband_core,

				ARRAY_SIZE(ar9462_2p0_baseband_core), 2);

		INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],

				ar9480_2p0_baseband_postamble,

				ARRAY_SIZE(ar9480_2p0_baseband_postamble), 5);

				ar9462_2p0_baseband_postamble,

				ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);



		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],

				ar9480_2p0_radio_core,

				ARRAY_SIZE(ar9480_2p0_radio_core), 2);

				ar9462_2p0_radio_core,

				ARRAY_SIZE(ar9462_2p0_radio_core), 2);

		INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],

				ar9480_2p0_radio_postamble,

				ARRAY_SIZE(ar9480_2p0_radio_postamble), 5);

				ar9462_2p0_radio_postamble,

				ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);

		INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,

				ar9480_2p0_radio_postamble_sys2ant,

				ARRAY_SIZE(ar9480_2p0_radio_postamble_sys2ant),

				ar9462_2p0_radio_postamble_sys2ant,

				ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),

				5);



		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],

				ar9480_2p0_soc_preamble,

				ARRAY_SIZE(ar9480_2p0_soc_preamble), 2);

				ar9462_2p0_soc_preamble,

				ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);

		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);

		INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],

				ar9480_2p0_soc_postamble,

				ARRAY_SIZE(ar9480_2p0_soc_postamble), 5);

				ar9462_2p0_soc_postamble,

				ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);



		INIT_INI_ARRAY(&ah->iniModesRxGain,

				ar9480_common_rx_gain_table_2p0,

				ARRAY_SIZE(ar9480_common_rx_gain_table_2p0), 2);

				ar9462_common_rx_gain_table_2p0,

				ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);



		INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR,

				ar9480_2p0_BTCOEX_MAX_TXPWR_table,

				ARRAY_SIZE(ar9480_2p0_BTCOEX_MAX_TXPWR_table),

				ar9462_2p0_BTCOEX_MAX_TXPWR_table,

				ARRAY_SIZE(ar9462_2p0_BTCOEX_MAX_TXPWR_table),

				2);



		/* Awake -> Sleep Setting */
@@ -380,15 +380,15 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 


		/* Fast clock modal settings */

		INIT_INI_ARRAY(&ah->iniModesAdditional,

				ar9480_modes_fast_clock_2p0,

				ARRAY_SIZE(ar9480_modes_fast_clock_2p0), 3);

				ar9462_modes_fast_clock_2p0,

				ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);



		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

				AR9480_BB_CTX_COEFJ(2p0),

				ARRAY_SIZE(AR9480_BB_CTX_COEFJ(2p0)), 2);

				AR9462_BB_CTX_COEFJ(2p0),

				ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);



		INIT_INI_ARRAY(&ah->ini_japan2484, AR9480_BBC_TXIFR_COEFFJ,

				ARRAY_SIZE(AR9480_BBC_TXIFR_COEFFJ), 2);

		INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,

				ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);



	} else if (AR_SREV_9580(ah)) {

		/* mac */
@@ -537,15 +537,15 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) 
			ar9580_1p0_lowest_ob_db_tx_gain_table,

			ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),

			5);

	else if (AR_SREV_9480_10(ah))

	else if (AR_SREV_9462_10(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			ar9480_modes_low_ob_db_tx_gain_table_1p0,

			ARRAY_SIZE(ar9480_modes_low_ob_db_tx_gain_table_1p0),

			ar9462_modes_low_ob_db_tx_gain_table_1p0,

			ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_1p0),

			5);

	else if (AR_SREV_9480_20(ah))

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			ar9480_modes_low_ob_db_tx_gain_table_2p0,

			ARRAY_SIZE(ar9480_modes_low_ob_db_tx_gain_table_2p0),

			ar9462_modes_low_ob_db_tx_gain_table_2p0,

			ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),

			5);

	else

		INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -581,15 +581,15 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) 
			ar9580_1p0_high_ob_db_tx_gain_table,

			ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),

			5);

	else if (AR_SREV_9480_10(ah))

	else if (AR_SREV_9462_10(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			ar9480_modes_high_ob_db_tx_gain_table_1p0,

			ARRAY_SIZE(ar9480_modes_high_ob_db_tx_gain_table_1p0),

			ar9462_modes_high_ob_db_tx_gain_table_1p0,

			ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_1p0),

			5);

	else if (AR_SREV_9480_20(ah))

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesTxGain,

			ar9480_modes_high_ob_db_tx_gain_table_2p0,

			ARRAY_SIZE(ar9480_modes_high_ob_db_tx_gain_table_2p0),

			ar9462_modes_high_ob_db_tx_gain_table_2p0,

			ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),

			5);

	else

		INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -712,15 +712,15 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) 
				ar9580_1p0_rx_gain_table,

				ARRAY_SIZE(ar9580_1p0_rx_gain_table),

				2);

	else if (AR_SREV_9480_10(ah))

	else if (AR_SREV_9462_10(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

				ar9480_common_rx_gain_table_1p0,

				ARRAY_SIZE(ar9480_common_rx_gain_table_1p0),

				ar9462_common_rx_gain_table_1p0,

				ARRAY_SIZE(ar9462_common_rx_gain_table_1p0),

				2);

	else if (AR_SREV_9480_20(ah))

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

				ar9480_common_rx_gain_table_2p0,

				ARRAY_SIZE(ar9480_common_rx_gain_table_2p0),

				ar9462_common_rx_gain_table_2p0,

				ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),

				2);

	else

		INIT_INI_ARRAY(&ah->iniModesRxGain,
@@ -751,15 +751,15 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 
			ar9485Common_wo_xlna_rx_gain_1_1,

			ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),

			2);

	else if (AR_SREV_9480_10(ah))

	else if (AR_SREV_9462_10(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			ar9480_common_wo_xlna_rx_gain_table_1p0,

			ARRAY_SIZE(ar9480_common_wo_xlna_rx_gain_table_1p0),

			ar9462_common_wo_xlna_rx_gain_table_1p0,

			ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_1p0),

			2);

	else if (AR_SREV_9480_20(ah))

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			ar9480_common_wo_xlna_rx_gain_table_2p0,

			ARRAY_SIZE(ar9480_common_wo_xlna_rx_gain_table_2p0),

			ar9462_common_wo_xlna_rx_gain_table_2p0,

			ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),

			2);

	else if (AR_SREV_9580(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,
@@ -775,14 +775,14 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 


static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)

{

	if (AR_SREV_9480_10(ah))

	if (AR_SREV_9462_10(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			ar9480_common_mixed_rx_gain_table_1p0,

			ARRAY_SIZE(ar9480_common_mixed_rx_gain_table_1p0), 2);

	else if (AR_SREV_9480_20(ah))

			ar9462_common_mixed_rx_gain_table_1p0,

			ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_1p0), 2);

	else if (AR_SREV_9462_20(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

			ar9480_common_mixed_rx_gain_table_2p0,

			ARRAY_SIZE(ar9480_common_mixed_rx_gain_table_2p0), 2);

			ar9462_common_mixed_rx_gain_table_2p0,

			ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);

}



static void ar9003_rx_gain_table_apply(struct ath_hw *ah)

drivers/net/wireless/ath/ath9k/ar9003_paprd.c

+3 −3
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah) 
		      AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28);

	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,

		      AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1);

	val = AR_SREV_9480(ah) ? 0x91 : 147;

	val = AR_SREV_9462(ah) ? 0x91 : 147;

	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL2,

		      AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, val);

	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
@@ -211,7 +211,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah) 
		      AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);

	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,

		      AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);

	if (AR_SREV_9485(ah) || AR_SREV_9480(ah))

	if (AR_SREV_9485(ah) || AR_SREV_9462(ah))

		REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,

			      AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,

			      -3);
@@ -219,7 +219,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah) 
		REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,

			      AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,

			      -6);

	val = AR_SREV_9480(ah) ? -10 : -15;

	val = AR_SREV_9462(ah) ? -10 : -15;

	REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,

		      AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE,

		      val);

drivers/net/wireless/ath/ath9k/ar9003_phy.c

+5 −5
Original line number Diff line number Diff line
@@ -559,7 +559,7 @@ static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) 


	if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))

		REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);

	else if (AR_SREV_9480(ah))

	else if (AR_SREV_9462(ah))

		/* xxx only when MCI support is enabled */

		REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);

	else
@@ -662,7 +662,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, 
		ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);

		ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);

		ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);

		if (i == ATH_INI_POST && AR_SREV_9480_20(ah))

		if (i == ATH_INI_POST && AR_SREV_9462_20(ah))

			ar9003_hw_prog_ini(ah,

					   &ah->ini_radio_post_sys2ant,

					   modesIndex);
@@ -685,7 +685,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, 
	if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)

		REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);



	if (AR_SREV_9480(ah))

	if (AR_SREV_9462(ah))

		ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1);



	ah->modes_index = modesIndex;
@@ -694,7 +694,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, 
	ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);

	ath9k_hw_apply_txpower(ah, chan);



	if (AR_SREV_9480(ah)) {

	if (AR_SREV_9462(ah)) {

		if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,

				AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))

			ah->enabled_cals |= TX_IQ_CAL;
@@ -1300,7 +1300,7 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah, 
	ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);

	ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);

	ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);

	if (AR_SREV_9480_20(ah))

	if (AR_SREV_9462_20(ah))

		ar9003_hw_prog_ini(ah,

				&ah->ini_radio_post_sys2ant,

				modesIndex);

drivers/net/wireless/ath/ath9k/ar9003_phy.h

+14 −14
Original line number Diff line number Diff line
@@ -325,10 +325,10 @@ 


#define AR_PHY_RX_OCGAIN        (AR_AGC_BASE + 0x200)



#define AR_PHY_CCA_NOM_VAL_9300_2GHZ          (AR_SREV_9480(ah) ? -127 : -110)

#define AR_PHY_CCA_NOM_VAL_9300_5GHZ          (AR_SREV_9480(ah) ? -127 : -115)

#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ     (AR_SREV_9480(ah) ? -127 : -125)

#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ     (AR_SREV_9480(ah) ? -127 : -125)

#define AR_PHY_CCA_NOM_VAL_9300_2GHZ          (AR_SREV_9462(ah) ? -127 : -110)

#define AR_PHY_CCA_NOM_VAL_9300_5GHZ          (AR_SREV_9462(ah) ? -127 : -115)

#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ     (AR_SREV_9462(ah) ? -127 : -125)

#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ     (AR_SREV_9462(ah) ? -127 : -125)

#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ     -95

#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ     -100
@@ -608,9 +608,9 @@ 
#define AR_PHY_AIC_CTRL_1_B0	(AR_SM_BASE + 0x4b4)

#define AR_PHY_AIC_CTRL_2_B0	(AR_SM_BASE + 0x4b8)

#define AR_PHY_AIC_CTRL_3_B0	(AR_SM_BASE + 0x4bc)

#define AR_PHY_AIC_STAT_0_B0	(AR_SM_BASE + (AR_SREV_9480_10(ah) ? \

#define AR_PHY_AIC_STAT_0_B0	(AR_SM_BASE + (AR_SREV_9462_10(ah) ? \

					0x4c0 : 0x4c4))

#define AR_PHY_AIC_STAT_1_B0	(AR_SM_BASE + (AR_SREV_9480_10(ah) ? \

#define AR_PHY_AIC_STAT_1_B0	(AR_SM_BASE + (AR_SREV_9462_10(ah) ? \

					0x4c4 : 0x4c8))

#define AR_PHY_AIC_CTRL_4_B0	(AR_SM_BASE + 0x4c0)

#define AR_PHY_AIC_STAT_2_B0	(AR_SM_BASE + 0x4cc)
@@ -625,7 +625,7 @@ 
#define AR_PHY_65NM_CH0_RXTX4       0x1610c



#define AR_CH0_TOP	(AR_SREV_9300(ah) ? 0x16288 : \

				((AR_SREV_9480(ah) ? 0x1628c : 0x16280)))

				((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))

#define AR_CH0_TOP_XPABIASLVL (0x300)

#define AR_CH0_TOP_XPABIASLVL_S (8)
@@ -638,8 +638,8 @@ 


#define AR_SWITCH_TABLE_COM_ALL (0xffff)

#define AR_SWITCH_TABLE_COM_ALL_S (0)

#define AR_SWITCH_TABLE_COM_AR9480_ALL (0xffffff)

#define AR_SWITCH_TABLE_COM_AR9480_ALL_S (0)

#define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)

#define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)

#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)

#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)

#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)
@@ -679,11 +679,11 @@ 
#define AR_CH0_XTAL_CAPOUTDAC	0x00fe0000

#define AR_CH0_XTAL_CAPOUTDAC_S	17



#define AR_PHY_PMU1		(AR_SREV_9480(ah) ? 0x16340 : 0x16c40)

#define AR_PHY_PMU1		(AR_SREV_9462(ah) ? 0x16340 : 0x16c40)

#define AR_PHY_PMU1_PWD		0x1

#define AR_PHY_PMU1_PWD_S	0



#define AR_PHY_PMU2		(AR_SREV_9480(ah) ? 0x16344 : 0x16c44)

#define AR_PHY_PMU2		(AR_SREV_9462(ah) ? 0x16344 : 0x16c44)

#define AR_PHY_PMU2_PGM		0x00200000

#define AR_PHY_PMU2_PGM_S	21
@@ -921,9 +921,9 @@ 
#define AR_PHY_AIC_CTRL_0_B1	(AR_SM1_BASE + 0x4b0)

#define AR_PHY_AIC_CTRL_1_B1	(AR_SM1_BASE + 0x4b4)

#define AR_PHY_AIC_CTRL_2_B1	(AR_SM1_BASE + 0x4b8)

#define AR_PHY_AIC_STAT_0_B1	(AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \

#define AR_PHY_AIC_STAT_0_B1	(AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \

					0x4c0 : 0x4c4))

#define AR_PHY_AIC_STAT_1_B1	(AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \

#define AR_PHY_AIC_STAT_1_B1	(AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \

					0x4c4 : 0x4c8))

#define AR_PHY_AIC_CTRL_4_B1	(AR_SM1_BASE + 0x4c0)

#define AR_PHY_AIC_STAT_2_B1	(AR_SM1_BASE + 0x4cc)
@@ -1001,7 +1001,7 @@ 
#define AR_GLB_BASE	0x20000

#define AR_PHY_GLB_CONTROL	(AR_GLB_BASE + 0x44)

#define AR_GLB_SCRATCH(_ah)	(AR_GLB_BASE + \

					(AR_SREV_9480_20(_ah) ? 0x4c : 0x50))

					(AR_SREV_9462_20(_ah) ? 0x4c : 0x50))

#define AR_GLB_STATUS		(AR_GLB_BASE + 0x48)



/*