Loading arch/arm/Kconfig +5 −0 Original line number Diff line number Diff line Loading @@ -69,6 +69,9 @@ config GENERIC_ISA_DMA config FIQ bool config ARCH_MTD_XIP bool source "init/Kconfig" menu "System Type" Loading Loading @@ -136,6 +139,7 @@ config ARCH_L7200 config ARCH_PXA bool "PXA2xx-based" select ARCH_MTD_XIP config ARCH_RPC bool "RiscPC" Loading @@ -152,6 +156,7 @@ config ARCH_SA1100 bool "SA1100-based" select ISA select ARCH_DISCONTIGMEM_ENABLE select ARCH_MTD_XIP config ARCH_S3C2410 bool "Samsung S3C2410" Loading arch/powerpc/kernel/signal_32.c +7 −11 Original line number Diff line number Diff line Loading @@ -142,11 +142,7 @@ static inline int get_old_sigaction(struct k_sigaction *new_ka, return 0; } static inline compat_uptr_t to_user_ptr(void *kp) { return (compat_uptr_t)(u64)kp; } #define to_user_ptr(p) ptr_to_compat(p) #define from_user_ptr(p) compat_ptr(p) static inline int save_general_regs(struct pt_regs *regs, Loading Loading @@ -213,8 +209,8 @@ static inline int get_old_sigaction(struct k_sigaction *new_ka, return 0; } #define to_user_ptr(p) (p) #define from_user_ptr(p) (p) #define to_user_ptr(p) ((unsigned long)(p)) #define from_user_ptr(p) ((void __user *)(p)) static inline int save_general_regs(struct pt_regs *regs, struct mcontext __user *frame) Loading Loading @@ -526,7 +522,7 @@ long compat_sys_rt_sigaction(int sig, const struct sigaction32 __user *act, ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); if (!ret && oact) { ret = put_user((long)old_ka.sa.sa_handler, &oact->sa_handler); ret = put_user(to_user_ptr(old_ka.sa.sa_handler), &oact->sa_handler); ret |= put_sigset_t(&oact->sa_mask, &old_ka.sa.sa_mask); ret |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags); } Loading Loading @@ -675,8 +671,8 @@ long compat_sys_rt_sigqueueinfo(u32 pid, u32 sig, compat_siginfo_t __user *uinfo int compat_sys_sigaltstack(u32 __new, u32 __old, int r5, int r6, int r7, int r8, struct pt_regs *regs) { stack_32_t __user * newstack = (stack_32_t __user *)(long) __new; stack_32_t __user * oldstack = (stack_32_t __user *)(long) __old; stack_32_t __user * newstack = compat_ptr(__new); stack_32_t __user * oldstack = compat_ptr(__old); stack_t uss, uoss; int ret; mm_segment_t old_fs; Loading Loading @@ -708,7 +704,7 @@ int compat_sys_sigaltstack(u32 __new, u32 __old, int r5, set_fs(old_fs); /* Copy the stack information to the user output buffer */ if (!ret && oldstack && (put_user((long)uoss.ss_sp, &oldstack->ss_sp) || (put_user(ptr_to_compat(uoss.ss_sp), &oldstack->ss_sp) || __put_user(uoss.ss_flags, &oldstack->ss_flags) || __put_user(uoss.ss_size, &oldstack->ss_size))) return -EFAULT; Loading arch/powerpc/kernel/signal_64.c +2 −2 Original line number Diff line number Diff line Loading @@ -60,8 +60,8 @@ struct rt_sigframe { struct ucontext uc; unsigned long _unused[2]; unsigned int tramp[TRAMP_SIZE]; struct siginfo *pinfo; void *puc; struct siginfo __user *pinfo; void __user *puc; struct siginfo info; /* 64 bit ABI allows for 288 bytes below sp before decrementing it. */ char abigap[288]; Loading arch/powerpc/platforms/powermac/pci.c +43 −46 Original line number Diff line number Diff line Loading @@ -136,14 +136,14 @@ static void __init fixup_bus_range(struct device_node *bridge) |(((unsigned int)(off)) & 0xFCUL) \ |1UL) static unsigned long macrisc_cfg_access(struct pci_controller* hose, static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset) { unsigned int caddr; if (bus == hose->first_busno) { if (dev_fn < (11 << 3)) return 0; return NULL; caddr = MACRISC_CFA0(dev_fn, offset); } else caddr = MACRISC_CFA1(bus, dev_fn, offset); Loading @@ -154,14 +154,14 @@ static unsigned long macrisc_cfg_access(struct pci_controller* hose, } while (in_le32(hose->cfg_addr) != caddr); offset &= has_uninorth ? 0x07 : 0x03; return ((unsigned long)hose->cfg_data) + offset; return hose->cfg_data + offset; } static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading @@ -177,13 +177,13 @@ static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: *val = in_8((u8 *)addr); *val = in_8(addr); break; case 2: *val = in_le16((u16 *)addr); *val = in_le16(addr); break; default: *val = in_le32((u32 *)addr); *val = in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading @@ -193,7 +193,7 @@ static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading @@ -209,16 +209,16 @@ static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: out_8((u8 *)addr, val); (void) in_8((u8 *)addr); out_8(addr, val); (void) in_8(addr); break; case 2: out_le16((u16 *)addr, val); (void) in_le16((u16 *)addr); out_le16(addr, val); (void) in_le16(addr); break; default: out_le32((u32 *)addr, val); (void) in_le32((u32 *)addr); out_le32(addr, val); (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading Loading @@ -348,25 +348,23 @@ static int u3_ht_skip_device(struct pci_controller *hose, + (((unsigned int)bus) << 16) \ + 0x01000000UL) static unsigned long u3_ht_cfg_access(struct pci_controller* hose, static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset) { if (bus == hose->first_busno) { /* For now, we don't self probe U3 HT bridge */ if (PCI_SLOT(devfn) == 0) return 0; return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset); return NULL; return hose->cfg_data + U3_HT_CFA0(devfn, offset); } else return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset); return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); } static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading Loading @@ -400,13 +398,13 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: *val = in_8((u8 *)addr); *val = in_8(addr); break; case 2: *val = in_le16((u16 *)addr); *val = in_le16(addr); break; default: *val = in_le32((u32 *)addr); *val = in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading @@ -416,7 +414,7 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading @@ -442,16 +440,16 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: out_8((u8 *)addr, val); (void) in_8((u8 *)addr); out_8(addr, val); (void) in_8(addr); break; case 2: out_le16((u16 *)addr, val); (void) in_le16((u16 *)addr); out_le16(addr, val); (void) in_le16(addr); break; default: out_le32((u32 *)addr, val); (void) in_le32((u32 *)addr); out_le32((u32 __iomem *)addr, val); (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading @@ -476,7 +474,7 @@ static struct pci_ops u3_ht_pci_ops = |(((unsigned int)(off)) & 0xfcU) \ |1UL) static unsigned long u4_pcie_cfg_access(struct pci_controller* hose, static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, int offset) { unsigned int caddr; Loading @@ -492,14 +490,14 @@ static unsigned long u4_pcie_cfg_access(struct pci_controller* hose, } while (in_le32(hose->cfg_addr) != caddr); offset &= 0x03; return ((unsigned long)hose->cfg_data) + offset; return hose->cfg_data + offset; } static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading @@ -515,13 +513,13 @@ static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: *val = in_8((u8 *)addr); *val = in_8(addr); break; case 2: *val = in_le16((u16 *)addr); *val = in_le16(addr); break; default: *val = in_le32((u32 *)addr); *val = in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading @@ -531,7 +529,7 @@ static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading @@ -547,16 +545,16 @@ static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: out_8((u8 *)addr, val); (void) in_8((u8 *)addr); out_8(addr, val); (void) in_8(addr); break; case 2: out_le16((u16 *)addr, val); (void) in_le16((u16 *)addr); out_le16(addr, val); (void) in_le16(addr); break; default: out_le32((u32 *)addr, val); (void) in_le32((u32 *)addr); out_le32(addr, val); (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading Loading @@ -773,8 +771,7 @@ static void __init setup_u3_ht(struct pci_controller* hose) * the reg address cell, we shall fix that by killing struct * reg_property and using some accessor functions instead */ hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000); hose->cfg_data = ioremap(0xf2000000, 0x02000000); /* * /ht node doesn't expose a "ranges" property, so we "remove" Loading arch/powerpc/sysdev/dart_iommu.c +1 −1 Original line number Diff line number Diff line Loading @@ -59,7 +59,7 @@ static unsigned long dart_tablesize; static u32 *dart_vbase; /* Mapped base address for the dart */ static unsigned int *__iomem dart; static unsigned int __iomem *dart; /* Dummy val that entries are set to when unused */ static unsigned int dart_emptyval; Loading Loading
arch/arm/Kconfig +5 −0 Original line number Diff line number Diff line Loading @@ -69,6 +69,9 @@ config GENERIC_ISA_DMA config FIQ bool config ARCH_MTD_XIP bool source "init/Kconfig" menu "System Type" Loading Loading @@ -136,6 +139,7 @@ config ARCH_L7200 config ARCH_PXA bool "PXA2xx-based" select ARCH_MTD_XIP config ARCH_RPC bool "RiscPC" Loading @@ -152,6 +156,7 @@ config ARCH_SA1100 bool "SA1100-based" select ISA select ARCH_DISCONTIGMEM_ENABLE select ARCH_MTD_XIP config ARCH_S3C2410 bool "Samsung S3C2410" Loading
arch/powerpc/kernel/signal_32.c +7 −11 Original line number Diff line number Diff line Loading @@ -142,11 +142,7 @@ static inline int get_old_sigaction(struct k_sigaction *new_ka, return 0; } static inline compat_uptr_t to_user_ptr(void *kp) { return (compat_uptr_t)(u64)kp; } #define to_user_ptr(p) ptr_to_compat(p) #define from_user_ptr(p) compat_ptr(p) static inline int save_general_regs(struct pt_regs *regs, Loading Loading @@ -213,8 +209,8 @@ static inline int get_old_sigaction(struct k_sigaction *new_ka, return 0; } #define to_user_ptr(p) (p) #define from_user_ptr(p) (p) #define to_user_ptr(p) ((unsigned long)(p)) #define from_user_ptr(p) ((void __user *)(p)) static inline int save_general_regs(struct pt_regs *regs, struct mcontext __user *frame) Loading Loading @@ -526,7 +522,7 @@ long compat_sys_rt_sigaction(int sig, const struct sigaction32 __user *act, ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL); if (!ret && oact) { ret = put_user((long)old_ka.sa.sa_handler, &oact->sa_handler); ret = put_user(to_user_ptr(old_ka.sa.sa_handler), &oact->sa_handler); ret |= put_sigset_t(&oact->sa_mask, &old_ka.sa.sa_mask); ret |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags); } Loading Loading @@ -675,8 +671,8 @@ long compat_sys_rt_sigqueueinfo(u32 pid, u32 sig, compat_siginfo_t __user *uinfo int compat_sys_sigaltstack(u32 __new, u32 __old, int r5, int r6, int r7, int r8, struct pt_regs *regs) { stack_32_t __user * newstack = (stack_32_t __user *)(long) __new; stack_32_t __user * oldstack = (stack_32_t __user *)(long) __old; stack_32_t __user * newstack = compat_ptr(__new); stack_32_t __user * oldstack = compat_ptr(__old); stack_t uss, uoss; int ret; mm_segment_t old_fs; Loading Loading @@ -708,7 +704,7 @@ int compat_sys_sigaltstack(u32 __new, u32 __old, int r5, set_fs(old_fs); /* Copy the stack information to the user output buffer */ if (!ret && oldstack && (put_user((long)uoss.ss_sp, &oldstack->ss_sp) || (put_user(ptr_to_compat(uoss.ss_sp), &oldstack->ss_sp) || __put_user(uoss.ss_flags, &oldstack->ss_flags) || __put_user(uoss.ss_size, &oldstack->ss_size))) return -EFAULT; Loading
arch/powerpc/kernel/signal_64.c +2 −2 Original line number Diff line number Diff line Loading @@ -60,8 +60,8 @@ struct rt_sigframe { struct ucontext uc; unsigned long _unused[2]; unsigned int tramp[TRAMP_SIZE]; struct siginfo *pinfo; void *puc; struct siginfo __user *pinfo; void __user *puc; struct siginfo info; /* 64 bit ABI allows for 288 bytes below sp before decrementing it. */ char abigap[288]; Loading
arch/powerpc/platforms/powermac/pci.c +43 −46 Original line number Diff line number Diff line Loading @@ -136,14 +136,14 @@ static void __init fixup_bus_range(struct device_node *bridge) |(((unsigned int)(off)) & 0xFCUL) \ |1UL) static unsigned long macrisc_cfg_access(struct pci_controller* hose, static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset) { unsigned int caddr; if (bus == hose->first_busno) { if (dev_fn < (11 << 3)) return 0; return NULL; caddr = MACRISC_CFA0(dev_fn, offset); } else caddr = MACRISC_CFA1(bus, dev_fn, offset); Loading @@ -154,14 +154,14 @@ static unsigned long macrisc_cfg_access(struct pci_controller* hose, } while (in_le32(hose->cfg_addr) != caddr); offset &= has_uninorth ? 0x07 : 0x03; return ((unsigned long)hose->cfg_data) + offset; return hose->cfg_data + offset; } static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading @@ -177,13 +177,13 @@ static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: *val = in_8((u8 *)addr); *val = in_8(addr); break; case 2: *val = in_le16((u16 *)addr); *val = in_le16(addr); break; default: *val = in_le32((u32 *)addr); *val = in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading @@ -193,7 +193,7 @@ static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading @@ -209,16 +209,16 @@ static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: out_8((u8 *)addr, val); (void) in_8((u8 *)addr); out_8(addr, val); (void) in_8(addr); break; case 2: out_le16((u16 *)addr, val); (void) in_le16((u16 *)addr); out_le16(addr, val); (void) in_le16(addr); break; default: out_le32((u32 *)addr, val); (void) in_le32((u32 *)addr); out_le32(addr, val); (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading Loading @@ -348,25 +348,23 @@ static int u3_ht_skip_device(struct pci_controller *hose, + (((unsigned int)bus) << 16) \ + 0x01000000UL) static unsigned long u3_ht_cfg_access(struct pci_controller* hose, static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset) { if (bus == hose->first_busno) { /* For now, we don't self probe U3 HT bridge */ if (PCI_SLOT(devfn) == 0) return 0; return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset); return NULL; return hose->cfg_data + U3_HT_CFA0(devfn, offset); } else return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset); return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); } static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading Loading @@ -400,13 +398,13 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: *val = in_8((u8 *)addr); *val = in_8(addr); break; case 2: *val = in_le16((u16 *)addr); *val = in_le16(addr); break; default: *val = in_le32((u32 *)addr); *val = in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading @@ -416,7 +414,7 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading @@ -442,16 +440,16 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: out_8((u8 *)addr, val); (void) in_8((u8 *)addr); out_8(addr, val); (void) in_8(addr); break; case 2: out_le16((u16 *)addr, val); (void) in_le16((u16 *)addr); out_le16(addr, val); (void) in_le16(addr); break; default: out_le32((u32 *)addr, val); (void) in_le32((u32 *)addr); out_le32((u32 __iomem *)addr, val); (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading @@ -476,7 +474,7 @@ static struct pci_ops u3_ht_pci_ops = |(((unsigned int)(off)) & 0xfcU) \ |1UL) static unsigned long u4_pcie_cfg_access(struct pci_controller* hose, static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, int offset) { unsigned int caddr; Loading @@ -492,14 +490,14 @@ static unsigned long u4_pcie_cfg_access(struct pci_controller* hose, } while (in_le32(hose->cfg_addr) != caddr); offset &= 0x03; return ((unsigned long)hose->cfg_data) + offset; return hose->cfg_data + offset; } static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading @@ -515,13 +513,13 @@ static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: *val = in_8((u8 *)addr); *val = in_8(addr); break; case 2: *val = in_le16((u16 *)addr); *val = in_le16(addr); break; default: *val = in_le32((u32 *)addr); *val = in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading @@ -531,7 +529,7 @@ static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { struct pci_controller *hose; unsigned long addr; volatile void __iomem *addr; hose = pci_bus_to_host(bus); if (hose == NULL) Loading @@ -547,16 +545,16 @@ static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, */ switch (len) { case 1: out_8((u8 *)addr, val); (void) in_8((u8 *)addr); out_8(addr, val); (void) in_8(addr); break; case 2: out_le16((u16 *)addr, val); (void) in_le16((u16 *)addr); out_le16(addr, val); (void) in_le16(addr); break; default: out_le32((u32 *)addr, val); (void) in_le32((u32 *)addr); out_le32(addr, val); (void) in_le32(addr); break; } return PCIBIOS_SUCCESSFUL; Loading Loading @@ -773,8 +771,7 @@ static void __init setup_u3_ht(struct pci_controller* hose) * the reg address cell, we shall fix that by killing struct * reg_property and using some accessor functions instead */ hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000); hose->cfg_data = ioremap(0xf2000000, 0x02000000); /* * /ht node doesn't expose a "ranges" property, so we "remove" Loading
arch/powerpc/sysdev/dart_iommu.c +1 −1 Original line number Diff line number Diff line Loading @@ -59,7 +59,7 @@ static unsigned long dart_tablesize; static u32 *dart_vbase; /* Mapped base address for the dart */ static unsigned int *__iomem dart; static unsigned int __iomem *dart; /* Dummy val that entries are set to when unused */ static unsigned int dart_emptyval; Loading